1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Brad Beckmann 30# Nilay Vaish 31 32import math 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from Ruby import create_topology 37 38# 39# Note: the L1 Cache latency is only used by the sequencer on fast path hits 40# 41class L0Cache(RubyCache): 42 latency = 1 43 44class L1Cache(RubyCache): 45 latency = 5 46 47# 48# Note: the L2 Cache latency is not currently used 49# 50class L2Cache(RubyCache): 51 latency = 15 52 53def define_options(parser): 54 parser.add_option("--num-clusters", type="int", default=1, 55 help="number of clusters in a design in which there are shared\ 56 caches private to clusters") 57 return 58 59def create_system(options, system, piobus, dma_ports, ruby_system): 60 61 if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 62 fatal("This script requires the MESI_Three_Level protocol to be built.") 63 64 cpu_sequencers = [] 65 66 # 67 # The ruby network creation expects the list of nodes in the system to be 68 # consistent with the NetDest list. Therefore the l1 controller nodes must be 69 # listed before the directory nodes and directory nodes before dma nodes, etc. 70 # 71 l0_cntrl_nodes = [] 72 l1_cntrl_nodes = [] 73 l2_cntrl_nodes = [] 74 dir_cntrl_nodes = [] 75 dma_cntrl_nodes = [] 76 77 assert (options.num_cpus % options.num_clusters == 0) 78 num_cpus_per_cluster = options.num_cpus / options.num_clusters 79 80 assert (options.num_l2caches % options.num_clusters == 0) 81 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 82 83 l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 84 block_size_bits = int(math.log(options.cacheline_size, 2)) 85 l2_index_start = block_size_bits + l2_bits 86 87 # 88 # Must create the individual controllers before the network to ensure the 89 # controller constructors are called before the network constructor 90 # 91 for i in xrange(options.num_clusters): 92 for j in xrange(num_cpus_per_cluster): 93 # 94 # First create the Ruby objects associated with this cpu 95 # 96 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 97 start_index_bit = block_size_bits, replacement_policy="LRU") 98 99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 100 start_index_bit = block_size_bits, replacement_policy="LRU") 101 102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 103 Icache = l0i_cache, Dcache = l0d_cache, 104 send_evictions = (options.cpu_type == "detailed"), 105 ruby_system = ruby_system) 106 107 cpu_seq = RubySequencer(version = i, icache = l0i_cache, 108 dcache = l0d_cache, ruby_system = ruby_system) 109 110 l0_cntrl.sequencer = cpu_seq 111 112 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 113 start_index_bit = block_size_bits, is_icache = False) 114 115 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 116 cache = l1_cache, l2_select_num_bits = l2_bits, 117 cluster_id = i, ruby_system = ruby_system) 118 119 if piobus != None:
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Brad Beckmann 30# Nilay Vaish 31 32import math 33import m5 34from m5.objects import * 35from m5.defines import buildEnv 36from Ruby import create_topology 37 38# 39# Note: the L1 Cache latency is only used by the sequencer on fast path hits 40# 41class L0Cache(RubyCache): 42 latency = 1 43 44class L1Cache(RubyCache): 45 latency = 5 46 47# 48# Note: the L2 Cache latency is not currently used 49# 50class L2Cache(RubyCache): 51 latency = 15 52 53def define_options(parser): 54 parser.add_option("--num-clusters", type="int", default=1, 55 help="number of clusters in a design in which there are shared\ 56 caches private to clusters") 57 return 58 59def create_system(options, system, piobus, dma_ports, ruby_system): 60 61 if buildEnv['PROTOCOL'] != 'MESI_Three_Level': 62 fatal("This script requires the MESI_Three_Level protocol to be built.") 63 64 cpu_sequencers = [] 65 66 # 67 # The ruby network creation expects the list of nodes in the system to be 68 # consistent with the NetDest list. Therefore the l1 controller nodes must be 69 # listed before the directory nodes and directory nodes before dma nodes, etc. 70 # 71 l0_cntrl_nodes = [] 72 l1_cntrl_nodes = [] 73 l2_cntrl_nodes = [] 74 dir_cntrl_nodes = [] 75 dma_cntrl_nodes = [] 76 77 assert (options.num_cpus % options.num_clusters == 0) 78 num_cpus_per_cluster = options.num_cpus / options.num_clusters 79 80 assert (options.num_l2caches % options.num_clusters == 0) 81 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters 82 83 l2_bits = int(math.log(num_l2caches_per_cluster, 2)) 84 block_size_bits = int(math.log(options.cacheline_size, 2)) 85 l2_index_start = block_size_bits + l2_bits 86 87 # 88 # Must create the individual controllers before the network to ensure the 89 # controller constructors are called before the network constructor 90 # 91 for i in xrange(options.num_clusters): 92 for j in xrange(num_cpus_per_cluster): 93 # 94 # First create the Ruby objects associated with this cpu 95 # 96 l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, 97 start_index_bit = block_size_bits, replacement_policy="LRU") 98 99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 100 start_index_bit = block_size_bits, replacement_policy="LRU") 101 102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 103 Icache = l0i_cache, Dcache = l0d_cache, 104 send_evictions = (options.cpu_type == "detailed"), 105 ruby_system = ruby_system) 106 107 cpu_seq = RubySequencer(version = i, icache = l0i_cache, 108 dcache = l0d_cache, ruby_system = ruby_system) 109 110 l0_cntrl.sequencer = cpu_seq 111 112 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 113 start_index_bit = block_size_bits, is_icache = False) 114 115 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, 116 cache = l1_cache, l2_select_num_bits = l2_bits, 117 cluster_id = i, ruby_system = ruby_system) 118 119 if piobus != None:
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121 122 exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 123 i*num_cpus_per_cluster+j)) 124 exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 125 i*num_cpus_per_cluster+j)) 126 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # 130 cpu_sequencers.append(cpu_seq) 131 l0_cntrl_nodes.append(l0_cntrl) 132 l1_cntrl_nodes.append(l1_cntrl) 133 l0_cntrl.peer = l1_cntrl 134 135 for j in xrange(num_l2caches_per_cluster): 136 l2_cache = L2Cache(size = options.l2_size, 137 assoc = options.l2_assoc, 138 start_index_bit = l2_index_start) 139 140 l2_cntrl = L2Cache_Controller( 141 version = i * num_l2caches_per_cluster + j, 142 L2cache = l2_cache, cluster_id = i, 143 transitions_per_cycle=options.ports, 144 ruby_system = ruby_system) 145 146 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 147 i * num_l2caches_per_cluster + j)) 148 l2_cntrl_nodes.append(l2_cntrl) 149 150 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 151 assert(phys_mem_size % options.num_dirs == 0) 152 mem_module_size = phys_mem_size / options.num_dirs 153 154 # Run each of the ruby memory controllers at a ratio of the frequency of 155 # the ruby system 156 # clk_divider value is a fix to pass regression. 157 ruby_system.memctrl_clk_domain = DerivedClockDomain( 158 clk_domain=ruby_system.clk_domain, 159 clk_divider=3) 160 161 for i in xrange(options.num_dirs): 162 # 163 # Create the Ruby objects associated with the directory controller 164 # 165 166 mem_cntrl = RubyMemoryControl( 167 clk_domain = ruby_system.memctrl_clk_domain, 168 version = i, 169 ruby_system = ruby_system) 170 171 dir_size = MemorySize('0B') 172 dir_size.value = mem_module_size 173 174 dir_cntrl = Directory_Controller(version = i, 175 directory = \ 176 RubyDirectoryMemory(version = i, 177 size = dir_size, 178 use_map = 179 options.use_map), 180 memBuffer = mem_cntrl, 181 transitions_per_cycle = options.ports, 182 ruby_system = ruby_system) 183 184 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 185 dir_cntrl_nodes.append(dir_cntrl) 186 187 for i, dma_port in enumerate(dma_ports): 188 # 189 # Create the Ruby objects associated with the dma controller 190 # 191 dma_seq = DMASequencer(version = i, 192 ruby_system = ruby_system) 193 194 dma_cntrl = DMA_Controller(version = i, 195 dma_sequencer = dma_seq, 196 transitions_per_cycle = options.ports, 197 ruby_system = ruby_system) 198 199 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 200 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 201 dma_cntrl_nodes.append(dma_cntrl) 202 203 all_cntrls = l0_cntrl_nodes + \ 204 l1_cntrl_nodes + \ 205 l2_cntrl_nodes + \ 206 dir_cntrl_nodes + \ 207 dma_cntrl_nodes 208 209 topology = create_topology(all_cntrls, options) 210 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 123 124 exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( 125 i*num_cpus_per_cluster+j)) 126 exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( 127 i*num_cpus_per_cluster+j)) 128 129 # 130 # Add controllers and sequencers to the appropriate lists 131 # 132 cpu_sequencers.append(cpu_seq) 133 l0_cntrl_nodes.append(l0_cntrl) 134 l1_cntrl_nodes.append(l1_cntrl) 135 l0_cntrl.peer = l1_cntrl 136 137 for j in xrange(num_l2caches_per_cluster): 138 l2_cache = L2Cache(size = options.l2_size, 139 assoc = options.l2_assoc, 140 start_index_bit = l2_index_start) 141 142 l2_cntrl = L2Cache_Controller( 143 version = i * num_l2caches_per_cluster + j, 144 L2cache = l2_cache, cluster_id = i, 145 transitions_per_cycle=options.ports, 146 ruby_system = ruby_system) 147 148 exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( 149 i * num_l2caches_per_cluster + j)) 150 l2_cntrl_nodes.append(l2_cntrl) 151 152 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 153 assert(phys_mem_size % options.num_dirs == 0) 154 mem_module_size = phys_mem_size / options.num_dirs 155 156 # Run each of the ruby memory controllers at a ratio of the frequency of 157 # the ruby system 158 # clk_divider value is a fix to pass regression. 159 ruby_system.memctrl_clk_domain = DerivedClockDomain( 160 clk_domain=ruby_system.clk_domain, 161 clk_divider=3) 162 163 for i in xrange(options.num_dirs): 164 # 165 # Create the Ruby objects associated with the directory controller 166 # 167 168 mem_cntrl = RubyMemoryControl( 169 clk_domain = ruby_system.memctrl_clk_domain, 170 version = i, 171 ruby_system = ruby_system) 172 173 dir_size = MemorySize('0B') 174 dir_size.value = mem_module_size 175 176 dir_cntrl = Directory_Controller(version = i, 177 directory = \ 178 RubyDirectoryMemory(version = i, 179 size = dir_size, 180 use_map = 181 options.use_map), 182 memBuffer = mem_cntrl, 183 transitions_per_cycle = options.ports, 184 ruby_system = ruby_system) 185 186 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 187 dir_cntrl_nodes.append(dir_cntrl) 188 189 for i, dma_port in enumerate(dma_ports): 190 # 191 # Create the Ruby objects associated with the dma controller 192 # 193 dma_seq = DMASequencer(version = i, 194 ruby_system = ruby_system) 195 196 dma_cntrl = DMA_Controller(version = i, 197 dma_sequencer = dma_seq, 198 transitions_per_cycle = options.ports, 199 ruby_system = ruby_system) 200 201 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 202 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 203 dma_cntrl_nodes.append(dma_cntrl) 204 205 all_cntrls = l0_cntrl_nodes + \ 206 l1_cntrl_nodes + \ 207 l2_cntrl_nodes + \ 208 dir_cntrl_nodes + \ 209 dma_cntrl_nodes 210 211 topology = create_topology(all_cntrls, options) 212 return (cpu_sequencers, dir_cntrl_nodes, topology)
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