MESI_Three_Level.py (10116:d61a59beb670) | MESI_Three_Level.py (10300:ed3816dae6d5) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 88 unchanged lines hidden (view full) --- 97 start_index_bit = block_size_bits, replacement_policy="LRU") 98 99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 100 start_index_bit = block_size_bits, replacement_policy="LRU") 101 102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 103 Icache = l0i_cache, Dcache = l0d_cache, 104 send_evictions = (options.cpu_type == "detailed"), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# Copyright (c) 2013 Mark D. Hill and David A. Wood 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 88 unchanged lines hidden (view full) --- 97 start_index_bit = block_size_bits, replacement_policy="LRU") 98 99 l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, 100 start_index_bit = block_size_bits, replacement_policy="LRU") 101 102 l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, 103 Icache = l0i_cache, Dcache = l0d_cache, 104 send_evictions = (options.cpu_type == "detailed"), |
105 clk_domain=system.cpu[i].clk_domain, |
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105 ruby_system = ruby_system) 106 107 cpu_seq = RubySequencer(version = i, icache = l0i_cache, | 106 ruby_system = ruby_system) 107 108 cpu_seq = RubySequencer(version = i, icache = l0i_cache, |
109 clk_domain=system.cpu[i].clk_domain, |
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108 dcache = l0d_cache, ruby_system = ruby_system) 109 110 l0_cntrl.sequencer = cpu_seq 111 112 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 113 start_index_bit = block_size_bits, is_icache = False) 114 115 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, --- 92 unchanged lines hidden --- | 110 dcache = l0d_cache, ruby_system = ruby_system) 111 112 l0_cntrl.sequencer = cpu_seq 113 114 l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 115 start_index_bit = block_size_bits, is_icache = False) 116 117 l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, --- 92 unchanged lines hidden --- |