1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
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124 i*num_cpus_per_cluster+j))
125
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l0_cntrl_nodes.append(l0_cntrl)
131 l1_cntrl_nodes.append(l1_cntrl)
132 l0_cntrl.peer = l1_cntrl
133
134 for j in xrange(num_l2caches_per_cluster):
135 l2_cache = L2Cache(size = options.l2_size,
136 assoc = options.l2_assoc,
137 start_index_bit = l2_index_start)
138
139 l2_cntrl = L2Cache_Controller(
140 version = i * num_l2caches_per_cluster + j,
141 L2cache = l2_cache, cluster_id = i,
142 transitions_per_cycle=options.ports,
143 ruby_system = ruby_system)
144
145 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
146 i * num_l2caches_per_cluster + j))
147 l2_cntrl_nodes.append(l2_cntrl)
148
149 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
150 assert(phys_mem_size % options.num_dirs == 0)
151 mem_module_size = phys_mem_size / options.num_dirs
152
153 # Run each of the ruby memory controllers at a ratio of the frequency of
154 # the ruby system
155 # clk_divider value is a fix to pass regression.
156 ruby_system.memctrl_clk_domain = DerivedClockDomain(
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178 options.use_map),
179 memBuffer = mem_cntrl,
180 transitions_per_cycle = options.ports,
181 ruby_system = ruby_system)
182
183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
184 dir_cntrl_nodes.append(dir_cntrl)
185
186 for i, dma_port in enumerate(dma_ports):
187 #
188 # Create the Ruby objects associated with the dma controller
189 #
190 dma_seq = DMASequencer(version = i,
191 ruby_system = ruby_system)
192
193 dma_cntrl = DMA_Controller(version = i,
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2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
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124 i*num_cpus_per_cluster+j))
125
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l0_cntrl_nodes.append(l0_cntrl)
131 l1_cntrl_nodes.append(l1_cntrl)
132 l0_cntrl.peer = l1_cntrl
133
134 for j in xrange(num_l2caches_per_cluster):
135 l2_cache = L2Cache(size = options.l2_size,
136 assoc = options.l2_assoc,
137 start_index_bit = l2_index_start)
138
139 l2_cntrl = L2Cache_Controller(
140 version = i * num_l2caches_per_cluster + j,
141 L2cache = l2_cache, cluster_id = i,
142 transitions_per_cycle=options.ports,
143 ruby_system = ruby_system)
144
145 exec("ruby_system.l2_cntrl%d = l2_cntrl" % (
146 i * num_l2caches_per_cluster + j))
147 l2_cntrl_nodes.append(l2_cntrl)
148
149 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
150 assert(phys_mem_size % options.num_dirs == 0)
151 mem_module_size = phys_mem_size / options.num_dirs
152
153 # Run each of the ruby memory controllers at a ratio of the frequency of
154 # the ruby system
155 # clk_divider value is a fix to pass regression.
156 ruby_system.memctrl_clk_domain = DerivedClockDomain(
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178 options.use_map),
179 memBuffer = mem_cntrl,
180 transitions_per_cycle = options.ports,
181 ruby_system = ruby_system)
182
183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
184 dir_cntrl_nodes.append(dir_cntrl)
185
186 for i, dma_port in enumerate(dma_ports):
187 #
188 # Create the Ruby objects associated with the dma controller
189 #
190 dma_seq = DMASequencer(version = i,
191 ruby_system = ruby_system)
192
193 dma_cntrl = DMA_Controller(version = i,
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