1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# Copyright (c) 2013 Mark D. Hill and David A. Wood
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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177 ruby_system.memctrl_clk_domain = DerivedClockDomain(
178 clk_domain=ruby_system.clk_domain,
179 clk_divider=3)
180
181 for i in xrange(options.num_dirs):
182 #
183 # Create the Ruby objects associated with the directory controller
184 #
185 dir_size = MemorySize('0B')
186 dir_size.value = mem_module_size
187
188 dir_cntrl = Directory_Controller(version = i,
189 directory = RubyDirectoryMemory(
190 version = i, size = dir_size),
191 transitions_per_cycle = options.ports,
192 ruby_system = ruby_system)
193
194 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
195 dir_cntrl_nodes.append(dir_cntrl)
196
197 # Connect the directory controllers and the network
198 dir_cntrl.requestToDir = ruby_system.network.master

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