1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# Copyright (c) 2016 Georgia Institute of Technology 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 87 unchanged lines hidden (view full) --- 96 97 # Connect the L1 controllers and the network 98 l1_cntrl.mandatoryQueue = MessageBuffer() 99 l1_cntrl.requestFromCache = MessageBuffer() 100 l1_cntrl.responseFromCache = MessageBuffer() 101 l1_cntrl.forwardFromCache = MessageBuffer() 102 103 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( |
104 options, bootmem, ruby_system, system) |
105 dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 106 if rom_dir_cntrl_node is not None: 107 dir_cntrl_nodes.append(rom_dir_cntrl_node) 108 for dir_cntrl in dir_cntrl_nodes: 109 # Connect the directory controllers and the network 110 dir_cntrl.requestToDir = MessageBuffer() 111 dir_cntrl.forwardToDir = MessageBuffer() 112 dir_cntrl.responseToDir = MessageBuffer() 113 114 115 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes 116 ruby_system.network.number_of_virtual_networks = 3 117 topology = create_topology(all_cntrls, options) 118 return (cpu_sequencers, mem_dir_cntrl_nodes, topology) |