| GPU_VIPER_Baseline.py (13400:cf74d21e948f) | GPU_VIPER_Baseline.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# --- 393 unchanged lines hidden (view full) --- 402 403 # For an odd number of CPUs, still create the right number of controllers 404 TCC_bits = int(math.log(options.num_tccs, 2)) 405 406 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 407 # Clusters 408 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 409 mainCluster = Cluster(intBW = crossbar_bw) | 1# Copyright (c) 2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# --- 393 unchanged lines hidden (view full) --- 402 403 # For an odd number of CPUs, still create the right number of controllers 404 TCC_bits = int(math.log(options.num_tccs, 2)) 405 406 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 407 # Clusters 408 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 409 mainCluster = Cluster(intBW = crossbar_bw) |
| 410 for i in xrange(options.num_dirs): | 410 for i in range(options.num_dirs): |
| 411 412 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 413 dir_cntrl.create(options, ruby_system, system) 414 dir_cntrl.number_of_TBEs = options.num_tbes 415 dir_cntrl.useL3OnWT = options.use_L3_on_WT 416 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 417 418 # Connect the Directory controller to the ruby network --- 16 unchanged lines hidden (view full) --- 435 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 436 dir_cntrl.responseFromMemory = MessageBuffer() 437 438 exec("system.dir_cntrl%d = dir_cntrl" % i) 439 dir_cntrl_nodes.append(dir_cntrl) 440 mainCluster.add(dir_cntrl) 441 442 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw) | 411 412 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 413 dir_cntrl.create(options, ruby_system, system) 414 dir_cntrl.number_of_TBEs = options.num_tbes 415 dir_cntrl.useL3OnWT = options.use_L3_on_WT 416 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 417 418 # Connect the Directory controller to the ruby network --- 16 unchanged lines hidden (view full) --- 435 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 436 dir_cntrl.responseFromMemory = MessageBuffer() 437 438 exec("system.dir_cntrl%d = dir_cntrl" % i) 439 dir_cntrl_nodes.append(dir_cntrl) 440 mainCluster.add(dir_cntrl) 441 442 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw) |
| 443 for i in xrange((options.num_cpus + 1) / 2): | 443 for i in range((options.num_cpus + 1) // 2): |
| 444 445 cp_cntrl = CPCntrl() 446 cp_cntrl.create(options, ruby_system, system) 447 448 exec("system.cp_cntrl%d = cp_cntrl" % i) 449 # 450 # Add controllers and sequencers to the appropriate lists 451 # --- 16 unchanged lines hidden (view full) --- 468 cp_cntrl.responseToCore.slave = ruby_system.network.master 469 470 cp_cntrl.mandatoryQueue = MessageBuffer() 471 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 472 473 cpuCluster.add(cp_cntrl) 474 475 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) | 444 445 cp_cntrl = CPCntrl() 446 cp_cntrl.create(options, ruby_system, system) 447 448 exec("system.cp_cntrl%d = cp_cntrl" % i) 449 # 450 # Add controllers and sequencers to the appropriate lists 451 # --- 16 unchanged lines hidden (view full) --- 468 cp_cntrl.responseToCore.slave = ruby_system.network.master 469 470 cp_cntrl.mandatoryQueue = MessageBuffer() 471 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 472 473 cpuCluster.add(cp_cntrl) 474 475 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) |
| 476 for i in xrange(options.num_compute_units): | 476 for i in range(options.num_compute_units): |
| 477 478 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 479 issue_latency = 1, 480 number_of_TBEs = 2560) 481 # TBEs set to max outstanding requests 482 tcp_cntrl.create(options, ruby_system, system) 483 tcp_cntrl.WB = options.WB_L1 484 tcp_cntrl.disableL1 = options.noL1 --- 20 unchanged lines hidden (view full) --- 505 506 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 507 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 508 509 tcp_cntrl.mandatoryQueue = MessageBuffer() 510 511 gpuCluster.add(tcp_cntrl) 512 | 477 478 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 479 issue_latency = 1, 480 number_of_TBEs = 2560) 481 # TBEs set to max outstanding requests 482 tcp_cntrl.create(options, ruby_system, system) 483 tcp_cntrl.WB = options.WB_L1 484 tcp_cntrl.disableL1 = options.noL1 --- 20 unchanged lines hidden (view full) --- 505 506 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 507 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 508 509 tcp_cntrl.mandatoryQueue = MessageBuffer() 510 511 gpuCluster.add(tcp_cntrl) 512 |
| 513 for i in xrange(options.num_sqc): | 513 for i in range(options.num_sqc): |
| 514 515 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 516 sqc_cntrl.create(options, ruby_system, system) 517 518 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 519 # 520 # Add controllers and sequencers to the appropriate lists 521 # --- 12 unchanged lines hidden (view full) --- 534 sqc_cntrl.mandatoryQueue = MessageBuffer() 535 536 # SQC also in GPU cluster 537 gpuCluster.add(sqc_cntrl) 538 539 # Because of wire buffers, num_tccs must equal num_tccdirs 540 numa_bit = 6 541 | 514 515 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 516 sqc_cntrl.create(options, ruby_system, system) 517 518 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 519 # 520 # Add controllers and sequencers to the appropriate lists 521 # --- 12 unchanged lines hidden (view full) --- 534 sqc_cntrl.mandatoryQueue = MessageBuffer() 535 536 # SQC also in GPU cluster 537 gpuCluster.add(sqc_cntrl) 538 539 # Because of wire buffers, num_tccs must equal num_tccdirs 540 numa_bit = 6 541 |
| 542 for i in xrange(options.num_tccs): | 542 for i in range(options.num_tccs): |
| 543 544 tcc_cntrl = TCCCntrl() 545 tcc_cntrl.create(options, ruby_system, system) 546 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 547 tcc_cntrl.l2_response_latency = options.TCC_latency 548 tcc_cntrl_nodes.append(tcc_cntrl) 549 tcc_cntrl.WB = options.WB_L2 550 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units --- 40 unchanged lines hidden --- | 543 544 tcc_cntrl = TCCCntrl() 545 tcc_cntrl.create(options, ruby_system, system) 546 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 547 tcc_cntrl.l2_response_latency = options.TCC_latency 548 tcc_cntrl_nodes.append(tcc_cntrl) 549 tcc_cntrl.WB = options.WB_L2 550 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units --- 40 unchanged lines hidden --- |