Cross Reference: /gem5/configs/ruby/GPU_VIPER

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GPU_VIPER_Baseline.py (13400:cf74d21e948f)	GPU_VIPER_Baseline.py (13731:67cd980cb20f)
1# Copyright (c) 2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# 9# 1. Redistributions of source code must retain the above copyright notice, 10# this list of conditions and the following disclaimer. 11# 12# 2. Redistributions in binary form must reproduce the above copyright notice, 13# this list of conditions and the following disclaimer in the documentation 14# and/or other materials provided with the distribution. 15# 16# 3. Neither the name of the copyright holder nor the names of its 17# contributors may be used to endorse or promote products derived from this 18# software without specific prior written permission. 19# 20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30# POSSIBILITY OF SUCH DAMAGE. 31# 32# Authors: Sooraj Puthoor 33 34import math 35import m5 36from m5.objects import * 37from m5.defines import buildEnv 38from m5.util import addToPath 39from Ruby import create_topology 40from Ruby import send_evicts 41 42addToPath('../') 43 44from topologies.Cluster import Cluster 45from topologies.Crossbar import Crossbar 46 47class CntrlBase: 48 _seqs = 0 49 @classmethod 50 def seqCount(cls): 51 # Use SeqCount not class since we need global count 52 CntrlBase._seqs += 1 53 return CntrlBase._seqs - 1 54 55 _cntrls = 0 56 @classmethod 57 def cntrlCount(cls): 58 # Use CntlCount not class since we need global count 59 CntrlBase._cntrls += 1 60 return CntrlBase._cntrls - 1 61 62 _version = 0 63 @classmethod 64 def versionCount(cls): 65 cls._version += 1 # Use count for this particular type 66 return cls._version - 1 67 68class L1Cache(RubyCache): 69 resourceStalls = False 70 dataArrayBanks = 2 71 tagArrayBanks = 2 72 dataAccessLatency = 1 73 tagAccessLatency = 1 74 def create(self, size, assoc, options): 75 self.size = MemorySize(size) 76 self.assoc = assoc 77 self.replacement_policy = PseudoLRUReplacementPolicy() 78 79class L2Cache(RubyCache): 80 resourceStalls = False 81 assoc = 16 82 dataArrayBanks = 16 83 tagArrayBanks = 16 84 def create(self, size, assoc, options): 85 self.size = MemorySize(size) 86 self.assoc = assoc 87 self.replacement_policy = PseudoLRUReplacementPolicy() 88 89class CPCntrl(CorePair_Controller, CntrlBase): 90 91 def create(self, options, ruby_system, system): 92 self.version = self.versionCount() 93 94 self.L1Icache = L1Cache() 95 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 96 self.L1D0cache = L1Cache() 97 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 98 self.L1D1cache = L1Cache() 99 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 100 self.L2cache = L2Cache() 101 self.L2cache.create(options.l2_size, options.l2_assoc, options) 102 103 self.sequencer = RubySequencer() 104 self.sequencer.version = self.seqCount() 105 self.sequencer.icache = self.L1Icache 106 self.sequencer.dcache = self.L1D0cache 107 self.sequencer.ruby_system = ruby_system 108 self.sequencer.coreid = 0 109 self.sequencer.is_cpu_sequencer = True 110 111 self.sequencer1 = RubySequencer() 112 self.sequencer1.version = self.seqCount() 113 self.sequencer1.icache = self.L1Icache 114 self.sequencer1.dcache = self.L1D1cache 115 self.sequencer1.ruby_system = ruby_system 116 self.sequencer1.coreid = 1 117 self.sequencer1.is_cpu_sequencer = True 118 119 self.issue_latency = options.cpu_to_dir_latency 120 self.send_evictions = send_evicts(options) 121 122 self.ruby_system = ruby_system 123 124 if options.recycle_latency: 125 self.recycle_latency = options.recycle_latency 126 127class TCPCache(RubyCache): 128 size = "16kB" 129 assoc = 16 130 dataArrayBanks = 16 131 tagArrayBanks = 16 132 dataAccessLatency = 4 133 tagAccessLatency = 1 134 def create(self, options): 135 self.size = MemorySize(options.tcp_size) 136 self.dataArrayBanks = 16 137 self.tagArrayBanks = 16 138 self.dataAccessLatency = 4 139 self.tagAccessLatency = 1 140 self.resourceStalls = options.no_tcc_resource_stalls 141 self.replacement_policy = PseudoLRUReplacementPolicy() 142 143class TCPCntrl(TCP_Controller, CntrlBase): 144 145 def create(self, options, ruby_system, system): 146 self.version = self.versionCount() 147 self.L1cache = TCPCache() 148 self.L1cache.create(options) 149 self.issue_latency = 1 150 151 self.coalescer = VIPERCoalescer() 152 self.coalescer.version = self.seqCount() 153 self.coalescer.icache = self.L1cache 154 self.coalescer.dcache = self.L1cache 155 self.coalescer.ruby_system = ruby_system 156 self.coalescer.support_inst_reqs = False 157 self.coalescer.is_cpu_sequencer = False 158 159 self.sequencer = RubySequencer() 160 self.sequencer.version = self.seqCount() 161 self.sequencer.icache = self.L1cache 162 self.sequencer.dcache = self.L1cache 163 self.sequencer.ruby_system = ruby_system 164 self.sequencer.is_cpu_sequencer = True 165 166 self.use_seq_not_coal = False 167 168 self.ruby_system = ruby_system 169 if options.recycle_latency: 170 self.recycle_latency = options.recycle_latency 171 172class SQCCache(RubyCache): 173 dataArrayBanks = 8 174 tagArrayBanks = 8 175 dataAccessLatency = 1 176 tagAccessLatency = 1 177 178 def create(self, options): 179 self.size = MemorySize(options.sqc_size) 180 self.assoc = options.sqc_assoc 181 self.replacement_policy = PseudoLRUReplacementPolicy() 182 183class SQCCntrl(SQC_Controller, CntrlBase): 184 185 def create(self, options, ruby_system, system): 186 self.version = self.versionCount() 187 self.L1cache = SQCCache() 188 self.L1cache.create(options) 189 self.L1cache.resourceStalls = False 190 self.sequencer = RubySequencer() 191 self.sequencer.version = self.seqCount() 192 self.sequencer.icache = self.L1cache 193 self.sequencer.dcache = self.L1cache 194 self.sequencer.ruby_system = ruby_system 195 self.sequencer.support_data_reqs = False 196 self.sequencer.is_cpu_sequencer = False 197 self.ruby_system = ruby_system 198 if options.recycle_latency: 199 self.recycle_latency = options.recycle_latency 200 201class TCC(RubyCache): 202 size = MemorySize("256kB") 203 assoc = 16 204 dataAccessLatency = 8 205 tagAccessLatency = 2 206 resourceStalls = True 207 def create(self, options): 208 self.assoc = options.tcc_assoc 209 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 210 s = options.num_compute_units 211 tcc_size = s * 128 212 tcc_size = str(tcc_size)+'kB' 213 self.size = MemorySize(tcc_size) 214 self.dataArrayBanks = 64 215 self.tagArrayBanks = 64 216 else: 217 self.size = MemorySize(options.tcc_size) 218 self.dataArrayBanks = 256 / options.num_tccs #number of data banks 219 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 220 self.size.value = self.size.value / options.num_tccs 221 if ((self.size.value / long(self.assoc)) < 128): 222 self.size.value = long(128 * self.assoc) 223 self.start_index_bit = math.log(options.cacheline_size, 2) + \ 224 math.log(options.num_tccs, 2) 225 self.replacement_policy = PseudoLRUReplacementPolicy() 226 227class TCCCntrl(TCC_Controller, CntrlBase): 228 def create(self, options, ruby_system, system): 229 self.version = self.versionCount() 230 self.L2cache = TCC() 231 self.L2cache.create(options) 232 self.ruby_system = ruby_system 233 self.L2cache.resourceStalls = options.no_tcc_resource_stalls 234 235 if options.recycle_latency: 236 self.recycle_latency = options.recycle_latency 237 238class L3Cache(RubyCache): 239 dataArrayBanks = 16 240 tagArrayBanks = 16 241 242 def create(self, options, ruby_system, system): 243 self.size = MemorySize(options.l3_size) 244 self.size.value /= options.num_dirs 245 self.assoc = options.l3_assoc 246 self.dataArrayBanks /= options.num_dirs 247 self.tagArrayBanks /= options.num_dirs 248 self.dataArrayBanks /= options.num_dirs 249 self.tagArrayBanks /= options.num_dirs 250 self.dataAccessLatency = options.l3_data_latency 251 self.tagAccessLatency = options.l3_tag_latency 252 self.resourceStalls = False 253 self.replacement_policy = PseudoLRUReplacementPolicy() 254 255class ProbeFilter(RubyCache): 256 size = "4MB" 257 assoc = 16 258 dataArrayBanks = 256 259 tagArrayBanks = 256 260 261 def create(self, options, ruby_system, system): 262 self.block_size = "%dB" % (64 * options.blocks_per_region) 263 self.size = options.region_dir_entries * \ 264 self.block_size * options.num_compute_units 265 self.assoc = 8 266 self.tagArrayBanks = 8 267 self.tagAccessLatency = options.dir_tag_latency 268 self.dataAccessLatency = 1 269 self.resourceStalls = options.no_resource_stalls 270 self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2)) 271 self.replacement_policy = PseudoLRUReplacementPolicy() 272 273class L3Cntrl(L3Cache_Controller, CntrlBase): 274 def create(self, options, ruby_system, system): 275 self.version = self.versionCount() 276 self.L3cache = L3Cache() 277 self.L3cache.create(options, ruby_system, system) 278 self.l3_response_latency = \ 279 max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 280 self.ruby_system = ruby_system 281 if options.recycle_latency: 282 self.recycle_latency = options.recycle_latency 283 284 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 285 req_to_l3, probe_to_l3, resp_to_l3): 286 self.reqToDir = req_to_dir 287 self.respToDir = resp_to_dir 288 self.l3UnblockToDir = l3_unblock_to_dir 289 self.reqToL3 = req_to_l3 290 self.probeToL3 = probe_to_l3 291 self.respToL3 = resp_to_l3 292 293class DirMem(RubyDirectoryMemory, CntrlBase): 294 def create(self, options, ruby_system, system): 295 self.version = self.versionCount() 296 297 phys_mem_size = AddrRange(options.mem_size).size() 298 mem_module_size = phys_mem_size / options.num_dirs 299 dir_size = MemorySize('0B') 300 dir_size.value = mem_module_size 301 self.size = dir_size 302 303class DirCntrl(Directory_Controller, CntrlBase): 304 def create(self, options, ruby_system, system): 305 self.version = self.versionCount() 306 self.response_latency = 30 307 self.directory = DirMem() 308 self.directory.create(options, ruby_system, system) 309 self.L3CacheMemory = L3Cache() 310 self.L3CacheMemory.create(options, ruby_system, system) 311 self.ProbeFilterMemory = ProbeFilter() 312 self.ProbeFilterMemory.create(options, ruby_system, system) 313 self.l3_hit_latency = \ 314 max(self.L3CacheMemory.dataAccessLatency, 315 self.L3CacheMemory.tagAccessLatency) 316 317 self.ruby_system = ruby_system 318 if options.recycle_latency: 319 self.recycle_latency = options.recycle_latency 320 321 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 322 req_to_l3, probe_to_l3, resp_to_l3): 323 self.reqToDir = req_to_dir 324 self.respToDir = resp_to_dir 325 self.l3UnblockToDir = l3_unblock_to_dir 326 self.reqToL3 = req_to_l3 327 self.probeToL3 = probe_to_l3 328 self.respToL3 = resp_to_l3 329 330def define_options(parser): 331 parser.add_option("--num-subcaches", type = "int", default = 4) 332 parser.add_option("--l3-data-latency", type = "int", default = 20) 333 parser.add_option("--l3-tag-latency", type = "int", default = 15) 334 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 335 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 336 parser.add_option("--no-resource-stalls", action = "store_false", 337 default = True) 338 parser.add_option("--no-tcc-resource-stalls", action = "store_false", 339 default = True) 340 parser.add_option("--num-tbes", type = "int", default = 2560) 341 parser.add_option("--l2-latency", type = "int", default = 50) # load to use 342 parser.add_option("--num-tccs", type = "int", default = 1, 343 help = "number of TCC banks in the GPU") 344 parser.add_option("--sqc-size", type = 'string', default = '32kB', 345 help = "SQC cache size") 346 parser.add_option("--sqc-assoc", type = 'int', default = 8, 347 help = "SQC cache assoc") 348 parser.add_option("--region-dir-entries", type = "int", default = 8192) 349 parser.add_option("--dir-tag-latency", type = "int", default = 8) 350 parser.add_option("--dir-tag-banks", type = "int", default = 4) 351 parser.add_option("--blocks-per-region", type = "int", default = 1) 352 parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 353 parser.add_option("--nonInclusiveDir", action = "store_true", 354 default = False) 355 parser.add_option("--WB_L1", action = "store_true", 356 default = False, help = "writeback L2") 357 parser.add_option("--WB_L2", action = "store_true", 358 default = False, help = "writeback L2") 359 parser.add_option("--TCP_latency", type = "int", 360 default = 4, help = "TCP latency") 361 parser.add_option("--TCC_latency", type = "int", 362 default = 16, help = "TCC latency") 363 parser.add_option("--tcc-size", type = 'string', default = '2MB', 364 help = "agregate tcc size") 365 parser.add_option("--tcc-assoc", type = 'int', default = 16, 366 help = "tcc assoc") 367 parser.add_option("--tcp-size", type = 'string', default = '16kB', 368 help = "tcp size") 369 parser.add_option("--sampler-sets", type = "int", default = 1024) 370 parser.add_option("--sampler-assoc", type = "int", default = 16) 371 parser.add_option("--sampler-counter", type = "int", default = 512) 372 parser.add_option("--noL1", action = "store_true", default = False, 373 help = "bypassL1") 374 parser.add_option("--noL2", action = "store_true", default = False, 375 help = "bypassL2") 376 377def create_system(options, full_system, system, dma_devices, bootmem, 378 ruby_system): 379 if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline': 380 panic("This script requires the" \ 381 "GPU_VIPER_Baseline protocol to be built.") 382 383 cpu_sequencers = [] 384 385 # 386 # The ruby network creation expects the list of nodes in the system to be 387 # consistent with the NetDest list. Therefore the l1 controller nodes 388 # must be listed before the directory nodes and directory nodes before 389 # dma nodes, etc. 390 # 391 cp_cntrl_nodes = [] 392 tcp_cntrl_nodes = [] 393 sqc_cntrl_nodes = [] 394 tcc_cntrl_nodes = [] 395 dir_cntrl_nodes = [] 396 l3_cntrl_nodes = [] 397 398 # 399 # Must create the individual controllers before the network to ensure the 400 # controller constructors are called before the network constructor 401 # 402 403 # For an odd number of CPUs, still create the right number of controllers 404 TCC_bits = int(math.log(options.num_tccs, 2)) 405 406 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 407 # Clusters 408 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 409 mainCluster = Cluster(intBW = crossbar_bw)	1# Copyright (c) 2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# 9# 1. Redistributions of source code must retain the above copyright notice, 10# this list of conditions and the following disclaimer. 11# 12# 2. Redistributions in binary form must reproduce the above copyright notice, 13# this list of conditions and the following disclaimer in the documentation 14# and/or other materials provided with the distribution. 15# 16# 3. Neither the name of the copyright holder nor the names of its 17# contributors may be used to endorse or promote products derived from this 18# software without specific prior written permission. 19# 20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30# POSSIBILITY OF SUCH DAMAGE. 31# 32# Authors: Sooraj Puthoor 33 34import math 35import m5 36from m5.objects import * 37from m5.defines import buildEnv 38from m5.util import addToPath 39from Ruby import create_topology 40from Ruby import send_evicts 41 42addToPath('../') 43 44from topologies.Cluster import Cluster 45from topologies.Crossbar import Crossbar 46 47class CntrlBase: 48 _seqs = 0 49 @classmethod 50 def seqCount(cls): 51 # Use SeqCount not class since we need global count 52 CntrlBase._seqs += 1 53 return CntrlBase._seqs - 1 54 55 _cntrls = 0 56 @classmethod 57 def cntrlCount(cls): 58 # Use CntlCount not class since we need global count 59 CntrlBase._cntrls += 1 60 return CntrlBase._cntrls - 1 61 62 _version = 0 63 @classmethod 64 def versionCount(cls): 65 cls._version += 1 # Use count for this particular type 66 return cls._version - 1 67 68class L1Cache(RubyCache): 69 resourceStalls = False 70 dataArrayBanks = 2 71 tagArrayBanks = 2 72 dataAccessLatency = 1 73 tagAccessLatency = 1 74 def create(self, size, assoc, options): 75 self.size = MemorySize(size) 76 self.assoc = assoc 77 self.replacement_policy = PseudoLRUReplacementPolicy() 78 79class L2Cache(RubyCache): 80 resourceStalls = False 81 assoc = 16 82 dataArrayBanks = 16 83 tagArrayBanks = 16 84 def create(self, size, assoc, options): 85 self.size = MemorySize(size) 86 self.assoc = assoc 87 self.replacement_policy = PseudoLRUReplacementPolicy() 88 89class CPCntrl(CorePair_Controller, CntrlBase): 90 91 def create(self, options, ruby_system, system): 92 self.version = self.versionCount() 93 94 self.L1Icache = L1Cache() 95 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 96 self.L1D0cache = L1Cache() 97 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 98 self.L1D1cache = L1Cache() 99 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 100 self.L2cache = L2Cache() 101 self.L2cache.create(options.l2_size, options.l2_assoc, options) 102 103 self.sequencer = RubySequencer() 104 self.sequencer.version = self.seqCount() 105 self.sequencer.icache = self.L1Icache 106 self.sequencer.dcache = self.L1D0cache 107 self.sequencer.ruby_system = ruby_system 108 self.sequencer.coreid = 0 109 self.sequencer.is_cpu_sequencer = True 110 111 self.sequencer1 = RubySequencer() 112 self.sequencer1.version = self.seqCount() 113 self.sequencer1.icache = self.L1Icache 114 self.sequencer1.dcache = self.L1D1cache 115 self.sequencer1.ruby_system = ruby_system 116 self.sequencer1.coreid = 1 117 self.sequencer1.is_cpu_sequencer = True 118 119 self.issue_latency = options.cpu_to_dir_latency 120 self.send_evictions = send_evicts(options) 121 122 self.ruby_system = ruby_system 123 124 if options.recycle_latency: 125 self.recycle_latency = options.recycle_latency 126 127class TCPCache(RubyCache): 128 size = "16kB" 129 assoc = 16 130 dataArrayBanks = 16 131 tagArrayBanks = 16 132 dataAccessLatency = 4 133 tagAccessLatency = 1 134 def create(self, options): 135 self.size = MemorySize(options.tcp_size) 136 self.dataArrayBanks = 16 137 self.tagArrayBanks = 16 138 self.dataAccessLatency = 4 139 self.tagAccessLatency = 1 140 self.resourceStalls = options.no_tcc_resource_stalls 141 self.replacement_policy = PseudoLRUReplacementPolicy() 142 143class TCPCntrl(TCP_Controller, CntrlBase): 144 145 def create(self, options, ruby_system, system): 146 self.version = self.versionCount() 147 self.L1cache = TCPCache() 148 self.L1cache.create(options) 149 self.issue_latency = 1 150 151 self.coalescer = VIPERCoalescer() 152 self.coalescer.version = self.seqCount() 153 self.coalescer.icache = self.L1cache 154 self.coalescer.dcache = self.L1cache 155 self.coalescer.ruby_system = ruby_system 156 self.coalescer.support_inst_reqs = False 157 self.coalescer.is_cpu_sequencer = False 158 159 self.sequencer = RubySequencer() 160 self.sequencer.version = self.seqCount() 161 self.sequencer.icache = self.L1cache 162 self.sequencer.dcache = self.L1cache 163 self.sequencer.ruby_system = ruby_system 164 self.sequencer.is_cpu_sequencer = True 165 166 self.use_seq_not_coal = False 167 168 self.ruby_system = ruby_system 169 if options.recycle_latency: 170 self.recycle_latency = options.recycle_latency 171 172class SQCCache(RubyCache): 173 dataArrayBanks = 8 174 tagArrayBanks = 8 175 dataAccessLatency = 1 176 tagAccessLatency = 1 177 178 def create(self, options): 179 self.size = MemorySize(options.sqc_size) 180 self.assoc = options.sqc_assoc 181 self.replacement_policy = PseudoLRUReplacementPolicy() 182 183class SQCCntrl(SQC_Controller, CntrlBase): 184 185 def create(self, options, ruby_system, system): 186 self.version = self.versionCount() 187 self.L1cache = SQCCache() 188 self.L1cache.create(options) 189 self.L1cache.resourceStalls = False 190 self.sequencer = RubySequencer() 191 self.sequencer.version = self.seqCount() 192 self.sequencer.icache = self.L1cache 193 self.sequencer.dcache = self.L1cache 194 self.sequencer.ruby_system = ruby_system 195 self.sequencer.support_data_reqs = False 196 self.sequencer.is_cpu_sequencer = False 197 self.ruby_system = ruby_system 198 if options.recycle_latency: 199 self.recycle_latency = options.recycle_latency 200 201class TCC(RubyCache): 202 size = MemorySize("256kB") 203 assoc = 16 204 dataAccessLatency = 8 205 tagAccessLatency = 2 206 resourceStalls = True 207 def create(self, options): 208 self.assoc = options.tcc_assoc 209 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 210 s = options.num_compute_units 211 tcc_size = s * 128 212 tcc_size = str(tcc_size)+'kB' 213 self.size = MemorySize(tcc_size) 214 self.dataArrayBanks = 64 215 self.tagArrayBanks = 64 216 else: 217 self.size = MemorySize(options.tcc_size) 218 self.dataArrayBanks = 256 / options.num_tccs #number of data banks 219 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 220 self.size.value = self.size.value / options.num_tccs 221 if ((self.size.value / long(self.assoc)) < 128): 222 self.size.value = long(128 * self.assoc) 223 self.start_index_bit = math.log(options.cacheline_size, 2) + \ 224 math.log(options.num_tccs, 2) 225 self.replacement_policy = PseudoLRUReplacementPolicy() 226 227class TCCCntrl(TCC_Controller, CntrlBase): 228 def create(self, options, ruby_system, system): 229 self.version = self.versionCount() 230 self.L2cache = TCC() 231 self.L2cache.create(options) 232 self.ruby_system = ruby_system 233 self.L2cache.resourceStalls = options.no_tcc_resource_stalls 234 235 if options.recycle_latency: 236 self.recycle_latency = options.recycle_latency 237 238class L3Cache(RubyCache): 239 dataArrayBanks = 16 240 tagArrayBanks = 16 241 242 def create(self, options, ruby_system, system): 243 self.size = MemorySize(options.l3_size) 244 self.size.value /= options.num_dirs 245 self.assoc = options.l3_assoc 246 self.dataArrayBanks /= options.num_dirs 247 self.tagArrayBanks /= options.num_dirs 248 self.dataArrayBanks /= options.num_dirs 249 self.tagArrayBanks /= options.num_dirs 250 self.dataAccessLatency = options.l3_data_latency 251 self.tagAccessLatency = options.l3_tag_latency 252 self.resourceStalls = False 253 self.replacement_policy = PseudoLRUReplacementPolicy() 254 255class ProbeFilter(RubyCache): 256 size = "4MB" 257 assoc = 16 258 dataArrayBanks = 256 259 tagArrayBanks = 256 260 261 def create(self, options, ruby_system, system): 262 self.block_size = "%dB" % (64 * options.blocks_per_region) 263 self.size = options.region_dir_entries * \ 264 self.block_size * options.num_compute_units 265 self.assoc = 8 266 self.tagArrayBanks = 8 267 self.tagAccessLatency = options.dir_tag_latency 268 self.dataAccessLatency = 1 269 self.resourceStalls = options.no_resource_stalls 270 self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2)) 271 self.replacement_policy = PseudoLRUReplacementPolicy() 272 273class L3Cntrl(L3Cache_Controller, CntrlBase): 274 def create(self, options, ruby_system, system): 275 self.version = self.versionCount() 276 self.L3cache = L3Cache() 277 self.L3cache.create(options, ruby_system, system) 278 self.l3_response_latency = \ 279 max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 280 self.ruby_system = ruby_system 281 if options.recycle_latency: 282 self.recycle_latency = options.recycle_latency 283 284 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 285 req_to_l3, probe_to_l3, resp_to_l3): 286 self.reqToDir = req_to_dir 287 self.respToDir = resp_to_dir 288 self.l3UnblockToDir = l3_unblock_to_dir 289 self.reqToL3 = req_to_l3 290 self.probeToL3 = probe_to_l3 291 self.respToL3 = resp_to_l3 292 293class DirMem(RubyDirectoryMemory, CntrlBase): 294 def create(self, options, ruby_system, system): 295 self.version = self.versionCount() 296 297 phys_mem_size = AddrRange(options.mem_size).size() 298 mem_module_size = phys_mem_size / options.num_dirs 299 dir_size = MemorySize('0B') 300 dir_size.value = mem_module_size 301 self.size = dir_size 302 303class DirCntrl(Directory_Controller, CntrlBase): 304 def create(self, options, ruby_system, system): 305 self.version = self.versionCount() 306 self.response_latency = 30 307 self.directory = DirMem() 308 self.directory.create(options, ruby_system, system) 309 self.L3CacheMemory = L3Cache() 310 self.L3CacheMemory.create(options, ruby_system, system) 311 self.ProbeFilterMemory = ProbeFilter() 312 self.ProbeFilterMemory.create(options, ruby_system, system) 313 self.l3_hit_latency = \ 314 max(self.L3CacheMemory.dataAccessLatency, 315 self.L3CacheMemory.tagAccessLatency) 316 317 self.ruby_system = ruby_system 318 if options.recycle_latency: 319 self.recycle_latency = options.recycle_latency 320 321 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 322 req_to_l3, probe_to_l3, resp_to_l3): 323 self.reqToDir = req_to_dir 324 self.respToDir = resp_to_dir 325 self.l3UnblockToDir = l3_unblock_to_dir 326 self.reqToL3 = req_to_l3 327 self.probeToL3 = probe_to_l3 328 self.respToL3 = resp_to_l3 329 330def define_options(parser): 331 parser.add_option("--num-subcaches", type = "int", default = 4) 332 parser.add_option("--l3-data-latency", type = "int", default = 20) 333 parser.add_option("--l3-tag-latency", type = "int", default = 15) 334 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 335 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 336 parser.add_option("--no-resource-stalls", action = "store_false", 337 default = True) 338 parser.add_option("--no-tcc-resource-stalls", action = "store_false", 339 default = True) 340 parser.add_option("--num-tbes", type = "int", default = 2560) 341 parser.add_option("--l2-latency", type = "int", default = 50) # load to use 342 parser.add_option("--num-tccs", type = "int", default = 1, 343 help = "number of TCC banks in the GPU") 344 parser.add_option("--sqc-size", type = 'string', default = '32kB', 345 help = "SQC cache size") 346 parser.add_option("--sqc-assoc", type = 'int', default = 8, 347 help = "SQC cache assoc") 348 parser.add_option("--region-dir-entries", type = "int", default = 8192) 349 parser.add_option("--dir-tag-latency", type = "int", default = 8) 350 parser.add_option("--dir-tag-banks", type = "int", default = 4) 351 parser.add_option("--blocks-per-region", type = "int", default = 1) 352 parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 353 parser.add_option("--nonInclusiveDir", action = "store_true", 354 default = False) 355 parser.add_option("--WB_L1", action = "store_true", 356 default = False, help = "writeback L2") 357 parser.add_option("--WB_L2", action = "store_true", 358 default = False, help = "writeback L2") 359 parser.add_option("--TCP_latency", type = "int", 360 default = 4, help = "TCP latency") 361 parser.add_option("--TCC_latency", type = "int", 362 default = 16, help = "TCC latency") 363 parser.add_option("--tcc-size", type = 'string', default = '2MB', 364 help = "agregate tcc size") 365 parser.add_option("--tcc-assoc", type = 'int', default = 16, 366 help = "tcc assoc") 367 parser.add_option("--tcp-size", type = 'string', default = '16kB', 368 help = "tcp size") 369 parser.add_option("--sampler-sets", type = "int", default = 1024) 370 parser.add_option("--sampler-assoc", type = "int", default = 16) 371 parser.add_option("--sampler-counter", type = "int", default = 512) 372 parser.add_option("--noL1", action = "store_true", default = False, 373 help = "bypassL1") 374 parser.add_option("--noL2", action = "store_true", default = False, 375 help = "bypassL2") 376 377def create_system(options, full_system, system, dma_devices, bootmem, 378 ruby_system): 379 if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline': 380 panic("This script requires the" \ 381 "GPU_VIPER_Baseline protocol to be built.") 382 383 cpu_sequencers = [] 384 385 # 386 # The ruby network creation expects the list of nodes in the system to be 387 # consistent with the NetDest list. Therefore the l1 controller nodes 388 # must be listed before the directory nodes and directory nodes before 389 # dma nodes, etc. 390 # 391 cp_cntrl_nodes = [] 392 tcp_cntrl_nodes = [] 393 sqc_cntrl_nodes = [] 394 tcc_cntrl_nodes = [] 395 dir_cntrl_nodes = [] 396 l3_cntrl_nodes = [] 397 398 # 399 # Must create the individual controllers before the network to ensure the 400 # controller constructors are called before the network constructor 401 # 402 403 # For an odd number of CPUs, still create the right number of controllers 404 TCC_bits = int(math.log(options.num_tccs, 2)) 405 406 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 407 # Clusters 408 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 409 mainCluster = Cluster(intBW = crossbar_bw)
410 for i in xrange(options.num_dirs):	410 for i in range(options.num_dirs):
411 412 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 413 dir_cntrl.create(options, ruby_system, system) 414 dir_cntrl.number_of_TBEs = options.num_tbes 415 dir_cntrl.useL3OnWT = options.use_L3_on_WT 416 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 417 418 # Connect the Directory controller to the ruby network 419 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 420 dir_cntrl.requestFromCores.slave = ruby_system.network.master 421 422 dir_cntrl.responseFromCores = MessageBuffer() 423 dir_cntrl.responseFromCores.slave = ruby_system.network.master 424 425 dir_cntrl.unblockFromCores = MessageBuffer() 426 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 427 428 dir_cntrl.probeToCore = MessageBuffer() 429 dir_cntrl.probeToCore.master = ruby_system.network.slave 430 431 dir_cntrl.responseToCore = MessageBuffer() 432 dir_cntrl.responseToCore.master = ruby_system.network.slave 433 434 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 435 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 436 dir_cntrl.responseFromMemory = MessageBuffer() 437 438 exec("system.dir_cntrl%d = dir_cntrl" % i) 439 dir_cntrl_nodes.append(dir_cntrl) 440 mainCluster.add(dir_cntrl) 441 442 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw)	411 412 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 413 dir_cntrl.create(options, ruby_system, system) 414 dir_cntrl.number_of_TBEs = options.num_tbes 415 dir_cntrl.useL3OnWT = options.use_L3_on_WT 416 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 417 418 # Connect the Directory controller to the ruby network 419 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 420 dir_cntrl.requestFromCores.slave = ruby_system.network.master 421 422 dir_cntrl.responseFromCores = MessageBuffer() 423 dir_cntrl.responseFromCores.slave = ruby_system.network.master 424 425 dir_cntrl.unblockFromCores = MessageBuffer() 426 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 427 428 dir_cntrl.probeToCore = MessageBuffer() 429 dir_cntrl.probeToCore.master = ruby_system.network.slave 430 431 dir_cntrl.responseToCore = MessageBuffer() 432 dir_cntrl.responseToCore.master = ruby_system.network.slave 433 434 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 435 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 436 dir_cntrl.responseFromMemory = MessageBuffer() 437 438 exec("system.dir_cntrl%d = dir_cntrl" % i) 439 dir_cntrl_nodes.append(dir_cntrl) 440 mainCluster.add(dir_cntrl) 441 442 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw)
443 for i in xrange((options.num_cpus + 1) / 2):	443 for i in range((options.num_cpus + 1) // 2):
444 445 cp_cntrl = CPCntrl() 446 cp_cntrl.create(options, ruby_system, system) 447 448 exec("system.cp_cntrl%d = cp_cntrl" % i) 449 # 450 # Add controllers and sequencers to the appropriate lists 451 # 452 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 453 454 # Connect the CP controllers and the network 455 cp_cntrl.requestFromCore = MessageBuffer() 456 cp_cntrl.requestFromCore.master = ruby_system.network.slave 457 458 cp_cntrl.responseFromCore = MessageBuffer() 459 cp_cntrl.responseFromCore.master = ruby_system.network.slave 460 461 cp_cntrl.unblockFromCore = MessageBuffer() 462 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 463 464 cp_cntrl.probeToCore = MessageBuffer() 465 cp_cntrl.probeToCore.slave = ruby_system.network.master 466 467 cp_cntrl.responseToCore = MessageBuffer() 468 cp_cntrl.responseToCore.slave = ruby_system.network.master 469 470 cp_cntrl.mandatoryQueue = MessageBuffer() 471 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 472 473 cpuCluster.add(cp_cntrl) 474 475 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)	444 445 cp_cntrl = CPCntrl() 446 cp_cntrl.create(options, ruby_system, system) 447 448 exec("system.cp_cntrl%d = cp_cntrl" % i) 449 # 450 # Add controllers and sequencers to the appropriate lists 451 # 452 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 453 454 # Connect the CP controllers and the network 455 cp_cntrl.requestFromCore = MessageBuffer() 456 cp_cntrl.requestFromCore.master = ruby_system.network.slave 457 458 cp_cntrl.responseFromCore = MessageBuffer() 459 cp_cntrl.responseFromCore.master = ruby_system.network.slave 460 461 cp_cntrl.unblockFromCore = MessageBuffer() 462 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 463 464 cp_cntrl.probeToCore = MessageBuffer() 465 cp_cntrl.probeToCore.slave = ruby_system.network.master 466 467 cp_cntrl.responseToCore = MessageBuffer() 468 cp_cntrl.responseToCore.slave = ruby_system.network.master 469 470 cp_cntrl.mandatoryQueue = MessageBuffer() 471 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 472 473 cpuCluster.add(cp_cntrl) 474 475 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
476 for i in xrange(options.num_compute_units):	476 for i in range(options.num_compute_units):
477 478 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 479 issue_latency = 1, 480 number_of_TBEs = 2560) 481 # TBEs set to max outstanding requests 482 tcp_cntrl.create(options, ruby_system, system) 483 tcp_cntrl.WB = options.WB_L1 484 tcp_cntrl.disableL1 = options.noL1 485 486 exec("system.tcp_cntrl%d = tcp_cntrl" % i) 487 # 488 # Add controllers and sequencers to the appropriate lists 489 # 490 cpu_sequencers.append(tcp_cntrl.coalescer) 491 tcp_cntrl_nodes.append(tcp_cntrl) 492 493 # Connect the CP (TCP) controllers to the ruby network 494 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 495 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 496 497 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 498 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 499 500 tcp_cntrl.unblockFromCore = MessageBuffer() 501 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 502 503 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 504 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 505 506 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 507 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 508 509 tcp_cntrl.mandatoryQueue = MessageBuffer() 510 511 gpuCluster.add(tcp_cntrl) 512	477 478 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 479 issue_latency = 1, 480 number_of_TBEs = 2560) 481 # TBEs set to max outstanding requests 482 tcp_cntrl.create(options, ruby_system, system) 483 tcp_cntrl.WB = options.WB_L1 484 tcp_cntrl.disableL1 = options.noL1 485 486 exec("system.tcp_cntrl%d = tcp_cntrl" % i) 487 # 488 # Add controllers and sequencers to the appropriate lists 489 # 490 cpu_sequencers.append(tcp_cntrl.coalescer) 491 tcp_cntrl_nodes.append(tcp_cntrl) 492 493 # Connect the CP (TCP) controllers to the ruby network 494 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 495 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 496 497 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 498 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 499 500 tcp_cntrl.unblockFromCore = MessageBuffer() 501 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 502 503 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 504 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 505 506 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 507 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 508 509 tcp_cntrl.mandatoryQueue = MessageBuffer() 510 511 gpuCluster.add(tcp_cntrl) 512
513 for i in xrange(options.num_sqc):	513 for i in range(options.num_sqc):
514 515 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 516 sqc_cntrl.create(options, ruby_system, system) 517 518 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 519 # 520 # Add controllers and sequencers to the appropriate lists 521 # 522 cpu_sequencers.append(sqc_cntrl.sequencer) 523 524 # Connect the SQC controller to the ruby network 525 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 526 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 527 528 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 529 sqc_cntrl.probeToSQC.slave = ruby_system.network.master 530 531 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 532 sqc_cntrl.responseToSQC.slave = ruby_system.network.master 533 534 sqc_cntrl.mandatoryQueue = MessageBuffer() 535 536 # SQC also in GPU cluster 537 gpuCluster.add(sqc_cntrl) 538 539 # Because of wire buffers, num_tccs must equal num_tccdirs 540 numa_bit = 6 541	514 515 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 516 sqc_cntrl.create(options, ruby_system, system) 517 518 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 519 # 520 # Add controllers and sequencers to the appropriate lists 521 # 522 cpu_sequencers.append(sqc_cntrl.sequencer) 523 524 # Connect the SQC controller to the ruby network 525 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 526 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 527 528 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 529 sqc_cntrl.probeToSQC.slave = ruby_system.network.master 530 531 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 532 sqc_cntrl.responseToSQC.slave = ruby_system.network.master 533 534 sqc_cntrl.mandatoryQueue = MessageBuffer() 535 536 # SQC also in GPU cluster 537 gpuCluster.add(sqc_cntrl) 538 539 # Because of wire buffers, num_tccs must equal num_tccdirs 540 numa_bit = 6 541
542 for i in xrange(options.num_tccs):	542 for i in range(options.num_tccs):
543 544 tcc_cntrl = TCCCntrl() 545 tcc_cntrl.create(options, ruby_system, system) 546 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 547 tcc_cntrl.l2_response_latency = options.TCC_latency 548 tcc_cntrl_nodes.append(tcc_cntrl) 549 tcc_cntrl.WB = options.WB_L2 550 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 551 552 # Connect the TCC controllers to the ruby network 553 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 554 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 555 556 tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 557 tcc_cntrl.responseToCore.master = ruby_system.network.slave 558 559 tcc_cntrl.probeFromNB = MessageBuffer() 560 tcc_cntrl.probeFromNB.slave = ruby_system.network.master 561 562 tcc_cntrl.responseFromNB = MessageBuffer() 563 tcc_cntrl.responseFromNB.slave = ruby_system.network.master 564 565 tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 566 tcc_cntrl.requestToNB.master = ruby_system.network.slave 567 568 tcc_cntrl.responseToNB = MessageBuffer() 569 tcc_cntrl.responseToNB.master = ruby_system.network.slave 570 571 tcc_cntrl.unblockToNB = MessageBuffer() 572 tcc_cntrl.unblockToNB.master = ruby_system.network.slave 573 574 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 575 576 exec("system.tcc_cntrl%d = tcc_cntrl" % i) 577 # connect all of the wire buffers between L3 and dirs up 578 # TCC cntrls added to the GPU cluster 579 gpuCluster.add(tcc_cntrl) 580 581 # Assuming no DMA devices 582 assert(len(dma_devices) == 0) 583 584 # Add cpu/gpu clusters to main cluster 585 mainCluster.add(cpuCluster) 586 mainCluster.add(gpuCluster) 587 588 ruby_system.network.number_of_virtual_networks = 10 589 590 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)	543 544 tcc_cntrl = TCCCntrl() 545 tcc_cntrl.create(options, ruby_system, system) 546 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 547 tcc_cntrl.l2_response_latency = options.TCC_latency 548 tcc_cntrl_nodes.append(tcc_cntrl) 549 tcc_cntrl.WB = options.WB_L2 550 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 551 552 # Connect the TCC controllers to the ruby network 553 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 554 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 555 556 tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 557 tcc_cntrl.responseToCore.master = ruby_system.network.slave 558 559 tcc_cntrl.probeFromNB = MessageBuffer() 560 tcc_cntrl.probeFromNB.slave = ruby_system.network.master 561 562 tcc_cntrl.responseFromNB = MessageBuffer() 563 tcc_cntrl.responseFromNB.slave = ruby_system.network.master 564 565 tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 566 tcc_cntrl.requestToNB.master = ruby_system.network.slave 567 568 tcc_cntrl.responseToNB = MessageBuffer() 569 tcc_cntrl.responseToNB.master = ruby_system.network.slave 570 571 tcc_cntrl.unblockToNB = MessageBuffer() 572 tcc_cntrl.unblockToNB.master = ruby_system.network.slave 573 574 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 575 576 exec("system.tcc_cntrl%d = tcc_cntrl" % i) 577 # connect all of the wire buffers between L3 and dirs up 578 # TCC cntrls added to the GPU cluster 579 gpuCluster.add(tcc_cntrl) 580 581 # Assuming no DMA devices 582 assert(len(dma_devices) == 0) 583 584 # Add cpu/gpu clusters to main cluster 585 mainCluster.add(cpuCluster) 586 mainCluster.add(gpuCluster) 587 588 ruby_system.network.number_of_virtual_networks = 10 589 590 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)