Cross Reference: /gem5/configs/ruby/GPU_VIPER

Deleted Added

sdiff udiff text old ( 11670:6ce719503eae ) new ( 12598:b80b2d9a251b )

full compact

GPU_VIPER_Baseline.py (11670:6ce719503eae)	GPU_VIPER_Baseline.py (12598:b80b2d9a251b)
1# 2# Copyright (c) 2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: 9# 10# 1. Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# 2. Redistributions in binary form must reproduce the above copyright notice, 14# this list of conditions and the following disclaimer in the documentation 15# and/or other materials provided with the distribution. 16# 17# 3. Neither the name of the copyright holder nor the names of its contributors 18# may be used to endorse or promote products derived from this software 19# without specific prior written permission. 20# 21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31# POSSIBILITY OF SUCH DAMAGE. 32# 33# Author: Sooraj Puthoor 34# 35 36import math 37import m5 38from m5.objects import * 39from m5.defines import buildEnv 40from Ruby import create_topology 41from Ruby import send_evicts 42 43from topologies.Cluster import Cluster 44from topologies.Crossbar import Crossbar 45 46class CntrlBase: 47 _seqs = 0 48 @classmethod 49 def seqCount(cls): 50 # Use SeqCount not class since we need global count 51 CntrlBase._seqs += 1 52 return CntrlBase._seqs - 1 53 54 _cntrls = 0 55 @classmethod 56 def cntrlCount(cls): 57 # Use CntlCount not class since we need global count 58 CntrlBase._cntrls += 1 59 return CntrlBase._cntrls - 1 60 61 _version = 0 62 @classmethod 63 def versionCount(cls): 64 cls._version += 1 # Use count for this particular type 65 return cls._version - 1 66 67class L1Cache(RubyCache): 68 resourceStalls = False 69 dataArrayBanks = 2 70 tagArrayBanks = 2 71 dataAccessLatency = 1 72 tagAccessLatency = 1 73 def create(self, size, assoc, options): 74 self.size = MemorySize(size) 75 self.assoc = assoc 76 self.replacement_policy = PseudoLRUReplacementPolicy() 77 78class L2Cache(RubyCache): 79 resourceStalls = False 80 assoc = 16 81 dataArrayBanks = 16 82 tagArrayBanks = 16 83 def create(self, size, assoc, options): 84 self.size = MemorySize(size) 85 self.assoc = assoc 86 self.replacement_policy = PseudoLRUReplacementPolicy() 87 88class CPCntrl(CorePair_Controller, CntrlBase): 89 90 def create(self, options, ruby_system, system): 91 self.version = self.versionCount() 92 93 self.L1Icache = L1Cache() 94 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 95 self.L1D0cache = L1Cache() 96 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 97 self.L1D1cache = L1Cache() 98 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 99 self.L2cache = L2Cache() 100 self.L2cache.create(options.l2_size, options.l2_assoc, options) 101 102 self.sequencer = RubySequencer() 103 self.sequencer.version = self.seqCount() 104 self.sequencer.icache = self.L1Icache 105 self.sequencer.dcache = self.L1D0cache 106 self.sequencer.ruby_system = ruby_system 107 self.sequencer.coreid = 0 108 self.sequencer.is_cpu_sequencer = True 109 110 self.sequencer1 = RubySequencer() 111 self.sequencer1.version = self.seqCount() 112 self.sequencer1.icache = self.L1Icache 113 self.sequencer1.dcache = self.L1D1cache 114 self.sequencer1.ruby_system = ruby_system 115 self.sequencer1.coreid = 1 116 self.sequencer1.is_cpu_sequencer = True 117 118 self.issue_latency = options.cpu_to_dir_latency 119 self.send_evictions = send_evicts(options) 120 121 self.ruby_system = ruby_system 122 123 if options.recycle_latency: 124 self.recycle_latency = options.recycle_latency 125 126class TCPCache(RubyCache): 127 size = "16kB" 128 assoc = 16 129 dataArrayBanks = 16 130 tagArrayBanks = 16 131 dataAccessLatency = 4 132 tagAccessLatency = 1 133 def create(self, options): 134 self.size = MemorySize(options.tcp_size) 135 self.dataArrayBanks = 16 136 self.tagArrayBanks = 16 137 self.dataAccessLatency = 4 138 self.tagAccessLatency = 1 139 self.resourceStalls = options.no_tcc_resource_stalls 140 self.replacement_policy = PseudoLRUReplacementPolicy() 141 142class TCPCntrl(TCP_Controller, CntrlBase): 143 144 def create(self, options, ruby_system, system): 145 self.version = self.versionCount() 146 self.L1cache = TCPCache() 147 self.L1cache.create(options) 148 self.issue_latency = 1 149 150 self.coalescer = VIPERCoalescer() 151 self.coalescer.version = self.seqCount() 152 self.coalescer.icache = self.L1cache 153 self.coalescer.dcache = self.L1cache 154 self.coalescer.ruby_system = ruby_system 155 self.coalescer.support_inst_reqs = False 156 self.coalescer.is_cpu_sequencer = False 157 158 self.sequencer = RubySequencer() 159 self.sequencer.version = self.seqCount() 160 self.sequencer.icache = self.L1cache 161 self.sequencer.dcache = self.L1cache 162 self.sequencer.ruby_system = ruby_system 163 self.sequencer.is_cpu_sequencer = True 164 165 self.use_seq_not_coal = False 166 167 self.ruby_system = ruby_system 168 if options.recycle_latency: 169 self.recycle_latency = options.recycle_latency 170 171class SQCCache(RubyCache): 172 dataArrayBanks = 8 173 tagArrayBanks = 8 174 dataAccessLatency = 1 175 tagAccessLatency = 1 176 177 def create(self, options): 178 self.size = MemorySize(options.sqc_size) 179 self.assoc = options.sqc_assoc 180 self.replacement_policy = PseudoLRUReplacementPolicy() 181 182class SQCCntrl(SQC_Controller, CntrlBase): 183 184 def create(self, options, ruby_system, system): 185 self.version = self.versionCount() 186 self.L1cache = SQCCache() 187 self.L1cache.create(options) 188 self.L1cache.resourceStalls = False 189 self.sequencer = RubySequencer() 190 self.sequencer.version = self.seqCount() 191 self.sequencer.icache = self.L1cache 192 self.sequencer.dcache = self.L1cache 193 self.sequencer.ruby_system = ruby_system 194 self.sequencer.support_data_reqs = False 195 self.sequencer.is_cpu_sequencer = False 196 self.ruby_system = ruby_system 197 if options.recycle_latency: 198 self.recycle_latency = options.recycle_latency 199 200class TCC(RubyCache): 201 size = MemorySize("256kB") 202 assoc = 16 203 dataAccessLatency = 8 204 tagAccessLatency = 2 205 resourceStalls = True 206 def create(self, options): 207 self.assoc = options.tcc_assoc 208 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 209 s = options.num_compute_units 210 tcc_size = s * 128 211 tcc_size = str(tcc_size)+'kB' 212 self.size = MemorySize(tcc_size) 213 self.dataArrayBanks = 64 214 self.tagArrayBanks = 64 215 else: 216 self.size = MemorySize(options.tcc_size) 217 self.dataArrayBanks = 256 / options.num_tccs #number of data banks 218 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 219 self.size.value = self.size.value / options.num_tccs 220 if ((self.size.value / long(self.assoc)) < 128): 221 self.size.value = long(128 * self.assoc) 222 self.start_index_bit = math.log(options.cacheline_size, 2) + \ 223 math.log(options.num_tccs, 2) 224 self.replacement_policy = PseudoLRUReplacementPolicy() 225 226class TCCCntrl(TCC_Controller, CntrlBase): 227 def create(self, options, ruby_system, system): 228 self.version = self.versionCount() 229 self.L2cache = TCC() 230 self.L2cache.create(options) 231 self.ruby_system = ruby_system 232 self.L2cache.resourceStalls = options.no_tcc_resource_stalls 233 234 if options.recycle_latency: 235 self.recycle_latency = options.recycle_latency 236 237class L3Cache(RubyCache): 238 dataArrayBanks = 16 239 tagArrayBanks = 16 240 241 def create(self, options, ruby_system, system): 242 self.size = MemorySize(options.l3_size) 243 self.size.value /= options.num_dirs 244 self.assoc = options.l3_assoc 245 self.dataArrayBanks /= options.num_dirs 246 self.tagArrayBanks /= options.num_dirs 247 self.dataArrayBanks /= options.num_dirs 248 self.tagArrayBanks /= options.num_dirs 249 self.dataAccessLatency = options.l3_data_latency 250 self.tagAccessLatency = options.l3_tag_latency 251 self.resourceStalls = False 252 self.replacement_policy = PseudoLRUReplacementPolicy() 253 254class ProbeFilter(RubyCache): 255 size = "4MB" 256 assoc = 16 257 dataArrayBanks = 256 258 tagArrayBanks = 256 259 260 def create(self, options, ruby_system, system): 261 self.block_size = "%dB" % (64 * options.blocks_per_region) 262 self.size = options.region_dir_entries * \ 263 self.block_size * options.num_compute_units 264 self.assoc = 8 265 self.tagArrayBanks = 8 266 self.tagAccessLatency = options.dir_tag_latency 267 self.dataAccessLatency = 1 268 self.resourceStalls = options.no_resource_stalls 269 self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2)) 270 self.replacement_policy = PseudoLRUReplacementPolicy() 271 272class L3Cntrl(L3Cache_Controller, CntrlBase): 273 def create(self, options, ruby_system, system): 274 self.version = self.versionCount() 275 self.L3cache = L3Cache() 276 self.L3cache.create(options, ruby_system, system) 277 self.l3_response_latency = \ 278 max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 279 self.ruby_system = ruby_system 280 if options.recycle_latency: 281 self.recycle_latency = options.recycle_latency 282 283 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 284 req_to_l3, probe_to_l3, resp_to_l3): 285 self.reqToDir = req_to_dir 286 self.respToDir = resp_to_dir 287 self.l3UnblockToDir = l3_unblock_to_dir 288 self.reqToL3 = req_to_l3 289 self.probeToL3 = probe_to_l3 290 self.respToL3 = resp_to_l3 291 292class DirMem(RubyDirectoryMemory, CntrlBase): 293 def create(self, options, ruby_system, system): 294 self.version = self.versionCount() 295 296 phys_mem_size = AddrRange(options.mem_size).size() 297 mem_module_size = phys_mem_size / options.num_dirs 298 dir_size = MemorySize('0B') 299 dir_size.value = mem_module_size 300 self.size = dir_size 301 302class DirCntrl(Directory_Controller, CntrlBase): 303 def create(self, options, ruby_system, system): 304 self.version = self.versionCount() 305 self.response_latency = 30 306 self.directory = DirMem() 307 self.directory.create(options, ruby_system, system) 308 self.L3CacheMemory = L3Cache() 309 self.L3CacheMemory.create(options, ruby_system, system) 310 self.ProbeFilterMemory = ProbeFilter() 311 self.ProbeFilterMemory.create(options, ruby_system, system) 312 self.l3_hit_latency = \ 313 max(self.L3CacheMemory.dataAccessLatency, 314 self.L3CacheMemory.tagAccessLatency) 315 316 self.ruby_system = ruby_system 317 if options.recycle_latency: 318 self.recycle_latency = options.recycle_latency 319 320 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 321 req_to_l3, probe_to_l3, resp_to_l3): 322 self.reqToDir = req_to_dir 323 self.respToDir = resp_to_dir 324 self.l3UnblockToDir = l3_unblock_to_dir 325 self.reqToL3 = req_to_l3 326 self.probeToL3 = probe_to_l3 327 self.respToL3 = resp_to_l3 328 329def define_options(parser): 330 parser.add_option("--num-subcaches", type = "int", default = 4) 331 parser.add_option("--l3-data-latency", type = "int", default = 20) 332 parser.add_option("--l3-tag-latency", type = "int", default = 15) 333 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 334 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 335 parser.add_option("--no-resource-stalls", action = "store_false", 336 default = True) 337 parser.add_option("--no-tcc-resource-stalls", action = "store_false", 338 default = True) 339 parser.add_option("--num-tbes", type = "int", default = 2560) 340 parser.add_option("--l2-latency", type = "int", default = 50) # load to use 341 parser.add_option("--num-tccs", type = "int", default = 1, 342 help = "number of TCC banks in the GPU") 343 parser.add_option("--sqc-size", type = 'string', default = '32kB', 344 help = "SQC cache size") 345 parser.add_option("--sqc-assoc", type = 'int', default = 8, 346 help = "SQC cache assoc") 347 parser.add_option("--region-dir-entries", type = "int", default = 8192) 348 parser.add_option("--dir-tag-latency", type = "int", default = 8) 349 parser.add_option("--dir-tag-banks", type = "int", default = 4) 350 parser.add_option("--blocks-per-region", type = "int", default = 1) 351 parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 352 parser.add_option("--nonInclusiveDir", action = "store_true", 353 default = False) 354 parser.add_option("--WB_L1", action = "store_true", 355 default = False, help = "writeback L2") 356 parser.add_option("--WB_L2", action = "store_true", 357 default = False, help = "writeback L2") 358 parser.add_option("--TCP_latency", type = "int", 359 default = 4, help = "TCP latency") 360 parser.add_option("--TCC_latency", type = "int", 361 default = 16, help = "TCC latency") 362 parser.add_option("--tcc-size", type = 'string', default = '2MB', 363 help = "agregate tcc size") 364 parser.add_option("--tcc-assoc", type = 'int', default = 16, 365 help = "tcc assoc") 366 parser.add_option("--tcp-size", type = 'string', default = '16kB', 367 help = "tcp size") 368 parser.add_option("--sampler-sets", type = "int", default = 1024) 369 parser.add_option("--sampler-assoc", type = "int", default = 16) 370 parser.add_option("--sampler-counter", type = "int", default = 512) 371 parser.add_option("--noL1", action = "store_true", default = False, 372 help = "bypassL1") 373 parser.add_option("--noL2", action = "store_true", default = False, 374 help = "bypassL2") 375	1# 2# Copyright (c) 2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: 9# 10# 1. Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# 2. Redistributions in binary form must reproduce the above copyright notice, 14# this list of conditions and the following disclaimer in the documentation 15# and/or other materials provided with the distribution. 16# 17# 3. Neither the name of the copyright holder nor the names of its contributors 18# may be used to endorse or promote products derived from this software 19# without specific prior written permission. 20# 21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31# POSSIBILITY OF SUCH DAMAGE. 32# 33# Author: Sooraj Puthoor 34# 35 36import math 37import m5 38from m5.objects import * 39from m5.defines import buildEnv 40from Ruby import create_topology 41from Ruby import send_evicts 42 43from topologies.Cluster import Cluster 44from topologies.Crossbar import Crossbar 45 46class CntrlBase: 47 _seqs = 0 48 @classmethod 49 def seqCount(cls): 50 # Use SeqCount not class since we need global count 51 CntrlBase._seqs += 1 52 return CntrlBase._seqs - 1 53 54 _cntrls = 0 55 @classmethod 56 def cntrlCount(cls): 57 # Use CntlCount not class since we need global count 58 CntrlBase._cntrls += 1 59 return CntrlBase._cntrls - 1 60 61 _version = 0 62 @classmethod 63 def versionCount(cls): 64 cls._version += 1 # Use count for this particular type 65 return cls._version - 1 66 67class L1Cache(RubyCache): 68 resourceStalls = False 69 dataArrayBanks = 2 70 tagArrayBanks = 2 71 dataAccessLatency = 1 72 tagAccessLatency = 1 73 def create(self, size, assoc, options): 74 self.size = MemorySize(size) 75 self.assoc = assoc 76 self.replacement_policy = PseudoLRUReplacementPolicy() 77 78class L2Cache(RubyCache): 79 resourceStalls = False 80 assoc = 16 81 dataArrayBanks = 16 82 tagArrayBanks = 16 83 def create(self, size, assoc, options): 84 self.size = MemorySize(size) 85 self.assoc = assoc 86 self.replacement_policy = PseudoLRUReplacementPolicy() 87 88class CPCntrl(CorePair_Controller, CntrlBase): 89 90 def create(self, options, ruby_system, system): 91 self.version = self.versionCount() 92 93 self.L1Icache = L1Cache() 94 self.L1Icache.create(options.l1i_size, options.l1i_assoc, options) 95 self.L1D0cache = L1Cache() 96 self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options) 97 self.L1D1cache = L1Cache() 98 self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options) 99 self.L2cache = L2Cache() 100 self.L2cache.create(options.l2_size, options.l2_assoc, options) 101 102 self.sequencer = RubySequencer() 103 self.sequencer.version = self.seqCount() 104 self.sequencer.icache = self.L1Icache 105 self.sequencer.dcache = self.L1D0cache 106 self.sequencer.ruby_system = ruby_system 107 self.sequencer.coreid = 0 108 self.sequencer.is_cpu_sequencer = True 109 110 self.sequencer1 = RubySequencer() 111 self.sequencer1.version = self.seqCount() 112 self.sequencer1.icache = self.L1Icache 113 self.sequencer1.dcache = self.L1D1cache 114 self.sequencer1.ruby_system = ruby_system 115 self.sequencer1.coreid = 1 116 self.sequencer1.is_cpu_sequencer = True 117 118 self.issue_latency = options.cpu_to_dir_latency 119 self.send_evictions = send_evicts(options) 120 121 self.ruby_system = ruby_system 122 123 if options.recycle_latency: 124 self.recycle_latency = options.recycle_latency 125 126class TCPCache(RubyCache): 127 size = "16kB" 128 assoc = 16 129 dataArrayBanks = 16 130 tagArrayBanks = 16 131 dataAccessLatency = 4 132 tagAccessLatency = 1 133 def create(self, options): 134 self.size = MemorySize(options.tcp_size) 135 self.dataArrayBanks = 16 136 self.tagArrayBanks = 16 137 self.dataAccessLatency = 4 138 self.tagAccessLatency = 1 139 self.resourceStalls = options.no_tcc_resource_stalls 140 self.replacement_policy = PseudoLRUReplacementPolicy() 141 142class TCPCntrl(TCP_Controller, CntrlBase): 143 144 def create(self, options, ruby_system, system): 145 self.version = self.versionCount() 146 self.L1cache = TCPCache() 147 self.L1cache.create(options) 148 self.issue_latency = 1 149 150 self.coalescer = VIPERCoalescer() 151 self.coalescer.version = self.seqCount() 152 self.coalescer.icache = self.L1cache 153 self.coalescer.dcache = self.L1cache 154 self.coalescer.ruby_system = ruby_system 155 self.coalescer.support_inst_reqs = False 156 self.coalescer.is_cpu_sequencer = False 157 158 self.sequencer = RubySequencer() 159 self.sequencer.version = self.seqCount() 160 self.sequencer.icache = self.L1cache 161 self.sequencer.dcache = self.L1cache 162 self.sequencer.ruby_system = ruby_system 163 self.sequencer.is_cpu_sequencer = True 164 165 self.use_seq_not_coal = False 166 167 self.ruby_system = ruby_system 168 if options.recycle_latency: 169 self.recycle_latency = options.recycle_latency 170 171class SQCCache(RubyCache): 172 dataArrayBanks = 8 173 tagArrayBanks = 8 174 dataAccessLatency = 1 175 tagAccessLatency = 1 176 177 def create(self, options): 178 self.size = MemorySize(options.sqc_size) 179 self.assoc = options.sqc_assoc 180 self.replacement_policy = PseudoLRUReplacementPolicy() 181 182class SQCCntrl(SQC_Controller, CntrlBase): 183 184 def create(self, options, ruby_system, system): 185 self.version = self.versionCount() 186 self.L1cache = SQCCache() 187 self.L1cache.create(options) 188 self.L1cache.resourceStalls = False 189 self.sequencer = RubySequencer() 190 self.sequencer.version = self.seqCount() 191 self.sequencer.icache = self.L1cache 192 self.sequencer.dcache = self.L1cache 193 self.sequencer.ruby_system = ruby_system 194 self.sequencer.support_data_reqs = False 195 self.sequencer.is_cpu_sequencer = False 196 self.ruby_system = ruby_system 197 if options.recycle_latency: 198 self.recycle_latency = options.recycle_latency 199 200class TCC(RubyCache): 201 size = MemorySize("256kB") 202 assoc = 16 203 dataAccessLatency = 8 204 tagAccessLatency = 2 205 resourceStalls = True 206 def create(self, options): 207 self.assoc = options.tcc_assoc 208 if hasattr(options, 'bw_scalor') and options.bw_scalor > 0: 209 s = options.num_compute_units 210 tcc_size = s * 128 211 tcc_size = str(tcc_size)+'kB' 212 self.size = MemorySize(tcc_size) 213 self.dataArrayBanks = 64 214 self.tagArrayBanks = 64 215 else: 216 self.size = MemorySize(options.tcc_size) 217 self.dataArrayBanks = 256 / options.num_tccs #number of data banks 218 self.tagArrayBanks = 256 / options.num_tccs #number of tag banks 219 self.size.value = self.size.value / options.num_tccs 220 if ((self.size.value / long(self.assoc)) < 128): 221 self.size.value = long(128 * self.assoc) 222 self.start_index_bit = math.log(options.cacheline_size, 2) + \ 223 math.log(options.num_tccs, 2) 224 self.replacement_policy = PseudoLRUReplacementPolicy() 225 226class TCCCntrl(TCC_Controller, CntrlBase): 227 def create(self, options, ruby_system, system): 228 self.version = self.versionCount() 229 self.L2cache = TCC() 230 self.L2cache.create(options) 231 self.ruby_system = ruby_system 232 self.L2cache.resourceStalls = options.no_tcc_resource_stalls 233 234 if options.recycle_latency: 235 self.recycle_latency = options.recycle_latency 236 237class L3Cache(RubyCache): 238 dataArrayBanks = 16 239 tagArrayBanks = 16 240 241 def create(self, options, ruby_system, system): 242 self.size = MemorySize(options.l3_size) 243 self.size.value /= options.num_dirs 244 self.assoc = options.l3_assoc 245 self.dataArrayBanks /= options.num_dirs 246 self.tagArrayBanks /= options.num_dirs 247 self.dataArrayBanks /= options.num_dirs 248 self.tagArrayBanks /= options.num_dirs 249 self.dataAccessLatency = options.l3_data_latency 250 self.tagAccessLatency = options.l3_tag_latency 251 self.resourceStalls = False 252 self.replacement_policy = PseudoLRUReplacementPolicy() 253 254class ProbeFilter(RubyCache): 255 size = "4MB" 256 assoc = 16 257 dataArrayBanks = 256 258 tagArrayBanks = 256 259 260 def create(self, options, ruby_system, system): 261 self.block_size = "%dB" % (64 * options.blocks_per_region) 262 self.size = options.region_dir_entries * \ 263 self.block_size * options.num_compute_units 264 self.assoc = 8 265 self.tagArrayBanks = 8 266 self.tagAccessLatency = options.dir_tag_latency 267 self.dataAccessLatency = 1 268 self.resourceStalls = options.no_resource_stalls 269 self.start_index_bit = 6 + int(math.log(options.blocks_per_region, 2)) 270 self.replacement_policy = PseudoLRUReplacementPolicy() 271 272class L3Cntrl(L3Cache_Controller, CntrlBase): 273 def create(self, options, ruby_system, system): 274 self.version = self.versionCount() 275 self.L3cache = L3Cache() 276 self.L3cache.create(options, ruby_system, system) 277 self.l3_response_latency = \ 278 max(self.L3cache.dataAccessLatency, self.L3cache.tagAccessLatency) 279 self.ruby_system = ruby_system 280 if options.recycle_latency: 281 self.recycle_latency = options.recycle_latency 282 283 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 284 req_to_l3, probe_to_l3, resp_to_l3): 285 self.reqToDir = req_to_dir 286 self.respToDir = resp_to_dir 287 self.l3UnblockToDir = l3_unblock_to_dir 288 self.reqToL3 = req_to_l3 289 self.probeToL3 = probe_to_l3 290 self.respToL3 = resp_to_l3 291 292class DirMem(RubyDirectoryMemory, CntrlBase): 293 def create(self, options, ruby_system, system): 294 self.version = self.versionCount() 295 296 phys_mem_size = AddrRange(options.mem_size).size() 297 mem_module_size = phys_mem_size / options.num_dirs 298 dir_size = MemorySize('0B') 299 dir_size.value = mem_module_size 300 self.size = dir_size 301 302class DirCntrl(Directory_Controller, CntrlBase): 303 def create(self, options, ruby_system, system): 304 self.version = self.versionCount() 305 self.response_latency = 30 306 self.directory = DirMem() 307 self.directory.create(options, ruby_system, system) 308 self.L3CacheMemory = L3Cache() 309 self.L3CacheMemory.create(options, ruby_system, system) 310 self.ProbeFilterMemory = ProbeFilter() 311 self.ProbeFilterMemory.create(options, ruby_system, system) 312 self.l3_hit_latency = \ 313 max(self.L3CacheMemory.dataAccessLatency, 314 self.L3CacheMemory.tagAccessLatency) 315 316 self.ruby_system = ruby_system 317 if options.recycle_latency: 318 self.recycle_latency = options.recycle_latency 319 320 def connectWireBuffers(self, req_to_dir, resp_to_dir, l3_unblock_to_dir, 321 req_to_l3, probe_to_l3, resp_to_l3): 322 self.reqToDir = req_to_dir 323 self.respToDir = resp_to_dir 324 self.l3UnblockToDir = l3_unblock_to_dir 325 self.reqToL3 = req_to_l3 326 self.probeToL3 = probe_to_l3 327 self.respToL3 = resp_to_l3 328 329def define_options(parser): 330 parser.add_option("--num-subcaches", type = "int", default = 4) 331 parser.add_option("--l3-data-latency", type = "int", default = 20) 332 parser.add_option("--l3-tag-latency", type = "int", default = 15) 333 parser.add_option("--cpu-to-dir-latency", type = "int", default = 120) 334 parser.add_option("--gpu-to-dir-latency", type = "int", default = 120) 335 parser.add_option("--no-resource-stalls", action = "store_false", 336 default = True) 337 parser.add_option("--no-tcc-resource-stalls", action = "store_false", 338 default = True) 339 parser.add_option("--num-tbes", type = "int", default = 2560) 340 parser.add_option("--l2-latency", type = "int", default = 50) # load to use 341 parser.add_option("--num-tccs", type = "int", default = 1, 342 help = "number of TCC banks in the GPU") 343 parser.add_option("--sqc-size", type = 'string', default = '32kB', 344 help = "SQC cache size") 345 parser.add_option("--sqc-assoc", type = 'int', default = 8, 346 help = "SQC cache assoc") 347 parser.add_option("--region-dir-entries", type = "int", default = 8192) 348 parser.add_option("--dir-tag-latency", type = "int", default = 8) 349 parser.add_option("--dir-tag-banks", type = "int", default = 4) 350 parser.add_option("--blocks-per-region", type = "int", default = 1) 351 parser.add_option("--use-L3-on-WT", action = "store_true", default = False) 352 parser.add_option("--nonInclusiveDir", action = "store_true", 353 default = False) 354 parser.add_option("--WB_L1", action = "store_true", 355 default = False, help = "writeback L2") 356 parser.add_option("--WB_L2", action = "store_true", 357 default = False, help = "writeback L2") 358 parser.add_option("--TCP_latency", type = "int", 359 default = 4, help = "TCP latency") 360 parser.add_option("--TCC_latency", type = "int", 361 default = 16, help = "TCC latency") 362 parser.add_option("--tcc-size", type = 'string', default = '2MB', 363 help = "agregate tcc size") 364 parser.add_option("--tcc-assoc", type = 'int', default = 16, 365 help = "tcc assoc") 366 parser.add_option("--tcp-size", type = 'string', default = '16kB', 367 help = "tcp size") 368 parser.add_option("--sampler-sets", type = "int", default = 1024) 369 parser.add_option("--sampler-assoc", type = "int", default = 16) 370 parser.add_option("--sampler-counter", type = "int", default = 512) 371 parser.add_option("--noL1", action = "store_true", default = False, 372 help = "bypassL1") 373 parser.add_option("--noL2", action = "store_true", default = False, 374 help = "bypassL2") 375
376def create_system(options, full_system, system, dma_devices, ruby_system):	376def create_system(options, full_system, system, dma_devices, bootmem, 377 ruby_system):
377 if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline': 378 panic("This script requires the" \ 379 "GPU_VIPER_Baseline protocol to be built.") 380 381 cpu_sequencers = [] 382 383 # 384 # The ruby network creation expects the list of nodes in the system to be 385 # consistent with the NetDest list. Therefore the l1 controller nodes 386 # must be listed before the directory nodes and directory nodes before 387 # dma nodes, etc. 388 # 389 cp_cntrl_nodes = [] 390 tcp_cntrl_nodes = [] 391 sqc_cntrl_nodes = [] 392 tcc_cntrl_nodes = [] 393 dir_cntrl_nodes = [] 394 l3_cntrl_nodes = [] 395 396 # 397 # Must create the individual controllers before the network to ensure the 398 # controller constructors are called before the network constructor 399 # 400 401 # For an odd number of CPUs, still create the right number of controllers 402 TCC_bits = int(math.log(options.num_tccs, 2)) 403 404 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 405 # Clusters 406 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 407 mainCluster = Cluster(intBW = crossbar_bw) 408 for i in xrange(options.num_dirs): 409 410 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 411 dir_cntrl.create(options, ruby_system, system) 412 dir_cntrl.number_of_TBEs = options.num_tbes 413 dir_cntrl.useL3OnWT = options.use_L3_on_WT 414 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 415 416 # Connect the Directory controller to the ruby network 417 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 418 dir_cntrl.requestFromCores.slave = ruby_system.network.master 419 420 dir_cntrl.responseFromCores = MessageBuffer() 421 dir_cntrl.responseFromCores.slave = ruby_system.network.master 422 423 dir_cntrl.unblockFromCores = MessageBuffer() 424 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 425 426 dir_cntrl.probeToCore = MessageBuffer() 427 dir_cntrl.probeToCore.master = ruby_system.network.slave 428 429 dir_cntrl.responseToCore = MessageBuffer() 430 dir_cntrl.responseToCore.master = ruby_system.network.slave 431 432 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 433 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 434 dir_cntrl.responseFromMemory = MessageBuffer() 435 436 exec("system.dir_cntrl%d = dir_cntrl" % i) 437 dir_cntrl_nodes.append(dir_cntrl) 438 mainCluster.add(dir_cntrl) 439 440 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw) 441 for i in xrange((options.num_cpus + 1) / 2): 442 443 cp_cntrl = CPCntrl() 444 cp_cntrl.create(options, ruby_system, system) 445 446 exec("system.cp_cntrl%d = cp_cntrl" % i) 447 # 448 # Add controllers and sequencers to the appropriate lists 449 # 450 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 451 452 # Connect the CP controllers and the network 453 cp_cntrl.requestFromCore = MessageBuffer() 454 cp_cntrl.requestFromCore.master = ruby_system.network.slave 455 456 cp_cntrl.responseFromCore = MessageBuffer() 457 cp_cntrl.responseFromCore.master = ruby_system.network.slave 458 459 cp_cntrl.unblockFromCore = MessageBuffer() 460 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 461 462 cp_cntrl.probeToCore = MessageBuffer() 463 cp_cntrl.probeToCore.slave = ruby_system.network.master 464 465 cp_cntrl.responseToCore = MessageBuffer() 466 cp_cntrl.responseToCore.slave = ruby_system.network.master 467 468 cp_cntrl.mandatoryQueue = MessageBuffer() 469 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 470 471 cpuCluster.add(cp_cntrl) 472 473 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 474 for i in xrange(options.num_compute_units): 475 476 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 477 issue_latency = 1, 478 number_of_TBEs = 2560) 479 # TBEs set to max outstanding requests 480 tcp_cntrl.create(options, ruby_system, system) 481 tcp_cntrl.WB = options.WB_L1 482 tcp_cntrl.disableL1 = options.noL1 483 484 exec("system.tcp_cntrl%d = tcp_cntrl" % i) 485 # 486 # Add controllers and sequencers to the appropriate lists 487 # 488 cpu_sequencers.append(tcp_cntrl.coalescer) 489 tcp_cntrl_nodes.append(tcp_cntrl) 490 491 # Connect the CP (TCP) controllers to the ruby network 492 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 493 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 494 495 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 496 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 497 498 tcp_cntrl.unblockFromCore = MessageBuffer() 499 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 500 501 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 502 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 503 504 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 505 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 506 507 tcp_cntrl.mandatoryQueue = MessageBuffer() 508 509 gpuCluster.add(tcp_cntrl) 510 511 for i in xrange(options.num_sqc): 512 513 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 514 sqc_cntrl.create(options, ruby_system, system) 515 516 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 517 # 518 # Add controllers and sequencers to the appropriate lists 519 # 520 cpu_sequencers.append(sqc_cntrl.sequencer) 521 522 # Connect the SQC controller to the ruby network 523 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 524 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 525 526 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 527 sqc_cntrl.probeToSQC.slave = ruby_system.network.master 528 529 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 530 sqc_cntrl.responseToSQC.slave = ruby_system.network.master 531 532 sqc_cntrl.mandatoryQueue = MessageBuffer() 533 534 # SQC also in GPU cluster 535 gpuCluster.add(sqc_cntrl) 536 537 # Because of wire buffers, num_tccs must equal num_tccdirs 538 numa_bit = 6 539 540 for i in xrange(options.num_tccs): 541 542 tcc_cntrl = TCCCntrl() 543 tcc_cntrl.create(options, ruby_system, system) 544 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 545 tcc_cntrl.l2_response_latency = options.TCC_latency 546 tcc_cntrl_nodes.append(tcc_cntrl) 547 tcc_cntrl.WB = options.WB_L2 548 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 549 550 # Connect the TCC controllers to the ruby network 551 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 552 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 553 554 tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 555 tcc_cntrl.responseToCore.master = ruby_system.network.slave 556 557 tcc_cntrl.probeFromNB = MessageBuffer() 558 tcc_cntrl.probeFromNB.slave = ruby_system.network.master 559 560 tcc_cntrl.responseFromNB = MessageBuffer() 561 tcc_cntrl.responseFromNB.slave = ruby_system.network.master 562 563 tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 564 tcc_cntrl.requestToNB.master = ruby_system.network.slave 565 566 tcc_cntrl.responseToNB = MessageBuffer() 567 tcc_cntrl.responseToNB.master = ruby_system.network.slave 568 569 tcc_cntrl.unblockToNB = MessageBuffer() 570 tcc_cntrl.unblockToNB.master = ruby_system.network.slave 571 572 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 573 574 exec("system.tcc_cntrl%d = tcc_cntrl" % i) 575 # connect all of the wire buffers between L3 and dirs up 576 # TCC cntrls added to the GPU cluster 577 gpuCluster.add(tcc_cntrl) 578 579 # Assuming no DMA devices 580 assert(len(dma_devices) == 0) 581 582 # Add cpu/gpu clusters to main cluster 583 mainCluster.add(cpuCluster) 584 mainCluster.add(gpuCluster) 585 586 ruby_system.network.number_of_virtual_networks = 10 587 588 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)	378 if buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline': 379 panic("This script requires the" \ 380 "GPU_VIPER_Baseline protocol to be built.") 381 382 cpu_sequencers = [] 383 384 # 385 # The ruby network creation expects the list of nodes in the system to be 386 # consistent with the NetDest list. Therefore the l1 controller nodes 387 # must be listed before the directory nodes and directory nodes before 388 # dma nodes, etc. 389 # 390 cp_cntrl_nodes = [] 391 tcp_cntrl_nodes = [] 392 sqc_cntrl_nodes = [] 393 tcc_cntrl_nodes = [] 394 dir_cntrl_nodes = [] 395 l3_cntrl_nodes = [] 396 397 # 398 # Must create the individual controllers before the network to ensure the 399 # controller constructors are called before the network constructor 400 # 401 402 # For an odd number of CPUs, still create the right number of controllers 403 TCC_bits = int(math.log(options.num_tccs, 2)) 404 405 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 406 # Clusters 407 crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock 408 mainCluster = Cluster(intBW = crossbar_bw) 409 for i in xrange(options.num_dirs): 410 411 dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits) 412 dir_cntrl.create(options, ruby_system, system) 413 dir_cntrl.number_of_TBEs = options.num_tbes 414 dir_cntrl.useL3OnWT = options.use_L3_on_WT 415 dir_cntrl.inclusiveDir = not options.nonInclusiveDir 416 417 # Connect the Directory controller to the ruby network 418 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 419 dir_cntrl.requestFromCores.slave = ruby_system.network.master 420 421 dir_cntrl.responseFromCores = MessageBuffer() 422 dir_cntrl.responseFromCores.slave = ruby_system.network.master 423 424 dir_cntrl.unblockFromCores = MessageBuffer() 425 dir_cntrl.unblockFromCores.slave = ruby_system.network.master 426 427 dir_cntrl.probeToCore = MessageBuffer() 428 dir_cntrl.probeToCore.master = ruby_system.network.slave 429 430 dir_cntrl.responseToCore = MessageBuffer() 431 dir_cntrl.responseToCore.master = ruby_system.network.slave 432 433 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) 434 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) 435 dir_cntrl.responseFromMemory = MessageBuffer() 436 437 exec("system.dir_cntrl%d = dir_cntrl" % i) 438 dir_cntrl_nodes.append(dir_cntrl) 439 mainCluster.add(dir_cntrl) 440 441 cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw) 442 for i in xrange((options.num_cpus + 1) / 2): 443 444 cp_cntrl = CPCntrl() 445 cp_cntrl.create(options, ruby_system, system) 446 447 exec("system.cp_cntrl%d = cp_cntrl" % i) 448 # 449 # Add controllers and sequencers to the appropriate lists 450 # 451 cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1]) 452 453 # Connect the CP controllers and the network 454 cp_cntrl.requestFromCore = MessageBuffer() 455 cp_cntrl.requestFromCore.master = ruby_system.network.slave 456 457 cp_cntrl.responseFromCore = MessageBuffer() 458 cp_cntrl.responseFromCore.master = ruby_system.network.slave 459 460 cp_cntrl.unblockFromCore = MessageBuffer() 461 cp_cntrl.unblockFromCore.master = ruby_system.network.slave 462 463 cp_cntrl.probeToCore = MessageBuffer() 464 cp_cntrl.probeToCore.slave = ruby_system.network.master 465 466 cp_cntrl.responseToCore = MessageBuffer() 467 cp_cntrl.responseToCore.slave = ruby_system.network.master 468 469 cp_cntrl.mandatoryQueue = MessageBuffer() 470 cp_cntrl.triggerQueue = MessageBuffer(ordered = True) 471 472 cpuCluster.add(cp_cntrl) 473 474 gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw) 475 for i in xrange(options.num_compute_units): 476 477 tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits, 478 issue_latency = 1, 479 number_of_TBEs = 2560) 480 # TBEs set to max outstanding requests 481 tcp_cntrl.create(options, ruby_system, system) 482 tcp_cntrl.WB = options.WB_L1 483 tcp_cntrl.disableL1 = options.noL1 484 485 exec("system.tcp_cntrl%d = tcp_cntrl" % i) 486 # 487 # Add controllers and sequencers to the appropriate lists 488 # 489 cpu_sequencers.append(tcp_cntrl.coalescer) 490 tcp_cntrl_nodes.append(tcp_cntrl) 491 492 # Connect the CP (TCP) controllers to the ruby network 493 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True) 494 tcp_cntrl.requestFromTCP.master = ruby_system.network.slave 495 496 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True) 497 tcp_cntrl.responseFromTCP.master = ruby_system.network.slave 498 499 tcp_cntrl.unblockFromCore = MessageBuffer() 500 tcp_cntrl.unblockFromCore.master = ruby_system.network.slave 501 502 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True) 503 tcp_cntrl.probeToTCP.slave = ruby_system.network.master 504 505 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True) 506 tcp_cntrl.responseToTCP.slave = ruby_system.network.master 507 508 tcp_cntrl.mandatoryQueue = MessageBuffer() 509 510 gpuCluster.add(tcp_cntrl) 511 512 for i in xrange(options.num_sqc): 513 514 sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits) 515 sqc_cntrl.create(options, ruby_system, system) 516 517 exec("system.sqc_cntrl%d = sqc_cntrl" % i) 518 # 519 # Add controllers and sequencers to the appropriate lists 520 # 521 cpu_sequencers.append(sqc_cntrl.sequencer) 522 523 # Connect the SQC controller to the ruby network 524 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True) 525 sqc_cntrl.requestFromSQC.master = ruby_system.network.slave 526 527 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True) 528 sqc_cntrl.probeToSQC.slave = ruby_system.network.master 529 530 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True) 531 sqc_cntrl.responseToSQC.slave = ruby_system.network.master 532 533 sqc_cntrl.mandatoryQueue = MessageBuffer() 534 535 # SQC also in GPU cluster 536 gpuCluster.add(sqc_cntrl) 537 538 # Because of wire buffers, num_tccs must equal num_tccdirs 539 numa_bit = 6 540 541 for i in xrange(options.num_tccs): 542 543 tcc_cntrl = TCCCntrl() 544 tcc_cntrl.create(options, ruby_system, system) 545 tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency 546 tcc_cntrl.l2_response_latency = options.TCC_latency 547 tcc_cntrl_nodes.append(tcc_cntrl) 548 tcc_cntrl.WB = options.WB_L2 549 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units 550 551 # Connect the TCC controllers to the ruby network 552 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True) 553 tcc_cntrl.requestFromTCP.slave = ruby_system.network.master 554 555 tcc_cntrl.responseToCore = MessageBuffer(ordered = True) 556 tcc_cntrl.responseToCore.master = ruby_system.network.slave 557 558 tcc_cntrl.probeFromNB = MessageBuffer() 559 tcc_cntrl.probeFromNB.slave = ruby_system.network.master 560 561 tcc_cntrl.responseFromNB = MessageBuffer() 562 tcc_cntrl.responseFromNB.slave = ruby_system.network.master 563 564 tcc_cntrl.requestToNB = MessageBuffer(ordered = True) 565 tcc_cntrl.requestToNB.master = ruby_system.network.slave 566 567 tcc_cntrl.responseToNB = MessageBuffer() 568 tcc_cntrl.responseToNB.master = ruby_system.network.slave 569 570 tcc_cntrl.unblockToNB = MessageBuffer() 571 tcc_cntrl.unblockToNB.master = ruby_system.network.slave 572 573 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True) 574 575 exec("system.tcc_cntrl%d = tcc_cntrl" % i) 576 # connect all of the wire buffers between L3 and dirs up 577 # TCC cntrls added to the GPU cluster 578 gpuCluster.add(tcc_cntrl) 579 580 # Assuming no DMA devices 581 assert(len(dma_devices) == 0) 582 583 # Add cpu/gpu clusters to main cluster 584 mainCluster.add(cpuCluster) 585 mainCluster.add(gpuCluster) 586 587 ruby_system.network.number_of_virtual_networks = 10 588 589 return (cpu_sequencers, dir_cntrl_nodes, mainCluster)