1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# --- 101 unchanged lines hidden (view full) --- 110 self.L1D0cache = L1DCache() 111 self.L1D0cache.create(options) 112 self.L1D1cache = L1DCache() 113 self.L1D1cache.create(options) 114 self.L2cache = L2Cache() 115 self.L2cache.create(options) 116 117 self.sequencer = RubySequencer() |
118 self.sequencer.version = self.seqCount() 119 self.sequencer.icache = self.L1Icache 120 self.sequencer.dcache = self.L1D0cache 121 self.sequencer.ruby_system = ruby_system 122 self.sequencer.coreid = 0 123 self.sequencer.is_cpu_sequencer = True 124 125 self.sequencer1 = RubySequencer() 126 self.sequencer1.version = self.seqCount() 127 self.sequencer1.icache = self.L1Icache 128 self.sequencer1.dcache = self.L1D1cache |
129 self.sequencer1.ruby_system = ruby_system 130 self.sequencer1.coreid = 1 131 self.sequencer1.is_cpu_sequencer = True 132 |
133 # Defines icache/dcache hit latency 134 self.mandatory_queue_latency = 2 135 |
136 self.issue_latency = options.cpu_to_dir_latency 137 self.send_evictions = send_evicts(options) 138 139 self.ruby_system = ruby_system 140 141 if options.recycle_latency: 142 self.recycle_latency = options.recycle_latency 143 --- 617 unchanged lines hidden --- |