1# 2# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: --- 357 unchanged lines hidden (view full) --- 366 req_to_l3, probe_to_l3, resp_to_l3): 367 self.reqToDir = req_to_dir 368 self.respToDir = resp_to_dir 369 self.l3UnblockToDir = l3_unblock_to_dir 370 self.reqToL3 = req_to_l3 371 self.probeToL3 = probe_to_l3 372 self.respToL3 = resp_to_l3 373 |
374class DirCntrl(Directory_Controller, CntrlBase): |
375 def create(self, options, dir_ranges, ruby_system, system): |
376 self.version = self.versionCount() 377 378 self.response_latency = 30 379 |
380 self.addr_ranges = dir_ranges 381 self.directory = RubyDirectoryMemory() |
382 383 self.L3CacheMemory = L3Cache() 384 self.L3CacheMemory.create(options, ruby_system, system) 385 386 self.l3_hit_latency = max(self.L3CacheMemory.dataAccessLatency, 387 self.L3CacheMemory.tagAccessLatency) 388 389 self.number_of_TBEs = options.num_tbes --- 62 unchanged lines hidden (view full) --- 452 # controller constructors are called before the network constructor 453 # 454 455 TCC_bits = int(math.log(options.num_tccs, 2)) 456 457 # This is the base crossbar that connects the L3s, Dirs, and cpu/gpu 458 # Clusters 459 mainCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s |
460 461 if options.numa_high_bit: 462 numa_bit = options.numa_high_bit 463 else: 464 # if the numa_bit is not specified, set the directory bits as the 465 # lowest bits above the block offset bits, and the numa_bit as the 466 # highest of those directory bits 467 dir_bits = int(math.log(options.num_dirs, 2)) 468 block_size_bits = int(math.log(options.cacheline_size, 2)) 469 numa_bit = block_size_bits + dir_bits - 1 470 |
471 for i in xrange(options.num_dirs): |
472 dir_ranges = [] 473 for r in system.mem_ranges: 474 addr_range = m5.objects.AddrRange(r.start, size = r.size(), 475 intlvHighBit = numa_bit, 476 intlvBits = dir_bits, 477 intlvMatch = i) 478 dir_ranges.append(addr_range) |
479 480 dir_cntrl = DirCntrl(TCC_select_num_bits = TCC_bits) |
481 dir_cntrl.create(options, dir_ranges, ruby_system, system) |
482 dir_cntrl.number_of_TBEs = 2560 * options.num_compute_units 483 #Enough TBEs for all TCP TBEs 484 485 # Connect the Directory controller to the ruby network 486 dir_cntrl.requestFromCores = MessageBuffer(ordered = True) 487 dir_cntrl.requestFromCores.slave = ruby_system.network.master 488 489 dir_cntrl.responseFromCores = MessageBuffer() --- 270 unchanged lines hidden --- |