1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#

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110 self.L1D0cache = L1DCache()
111 self.L1D0cache.create(options)
112 self.L1D1cache = L1DCache()
113 self.L1D1cache.create(options)
114 self.L2cache = L2Cache()
115 self.L2cache.create(options)
116
117 self.sequencer = RubySequencer()
118 self.sequencer.icache_hit_latency = 2
119 self.sequencer.dcache_hit_latency = 2
120 self.sequencer.version = self.seqCount()
121 self.sequencer.icache = self.L1Icache
122 self.sequencer.dcache = self.L1D0cache
123 self.sequencer.ruby_system = ruby_system
124 self.sequencer.coreid = 0
125 self.sequencer.is_cpu_sequencer = True
126
127 self.sequencer1 = RubySequencer()
128 self.sequencer1.version = self.seqCount()
129 self.sequencer1.icache = self.L1Icache
130 self.sequencer1.dcache = self.L1D1cache
131 self.sequencer1.icache_hit_latency = 2
132 self.sequencer1.dcache_hit_latency = 2
133 self.sequencer1.ruby_system = ruby_system
134 self.sequencer1.coreid = 1
135 self.sequencer1.is_cpu_sequencer = True
136
137 self.issue_latency = options.cpu_to_dir_latency
138 self.send_evictions = send_evicts(options)
139
140 self.ruby_system = ruby_system
141
142 if options.recycle_latency:
143 self.recycle_latency = options.recycle_latency
144

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