1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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40from __future__ import print_function
41from __future__ import absolute_import
42
43# import the m5 (gem5) library created when gem5 is built
44import m5
45# import all of the SimObjects
46from m5.objects import *
47
48# You can import ruby_caches_MI_example to use the MI_example protocol instead
49# of the MSI protocol
50from msi_caches import MyCacheSystem
51
52# create the system we are going to simulate
53system = System()
54
55# Set the clock fequency of the system (and all of its children)

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90# Set the command
91# cmd is a list which begins with the executable (like argv)
92process.cmd = [binary]
93# Set the cpu to use the process as its workload and create thread contexts
94for cpu in system.cpu:
95 cpu.workload = process
96 cpu.createThreads()
97
98# set up the root SimObject and start the simulation
99root = Root(full_system = False, system = system)
100# instantiate all of the objects we've created above
101m5.instantiate()
102
103print("Beginning simulation!")
104exit_event = m5.simulate()
105print('Exiting @ tick {} because {}'.format(
106 m5.curTick(), exit_event.getCause())
107 )