simple.py (11104:2d537040a4b9) | simple.py (11154:fce93f1c885b) |
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1# -*- coding: utf-8 -*- 2# Copyright (c) 2015 Jason Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 56 unchanged lines hidden (view full) --- 65system.cpu.dcache_port = system.membus.slave 66 67# create the interrupt controller for the CPU and connect to the membus 68system.cpu.createInterruptController() 69 70# For x86 only, make sure the interrupts are connected to the memory 71# Note: these are directly connected to the memory bus and are not cached 72if m5.defines.buildEnv['TARGET_ISA'] == "x86": | 1# -*- coding: utf-8 -*- 2# Copyright (c) 2015 Jason Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 56 unchanged lines hidden (view full) --- 65system.cpu.dcache_port = system.membus.slave 66 67# create the interrupt controller for the CPU and connect to the membus 68system.cpu.createInterruptController() 69 70# For x86 only, make sure the interrupts are connected to the memory 71# Note: these are directly connected to the memory bus and are not cached 72if m5.defines.buildEnv['TARGET_ISA'] == "x86": |
73 system.cpu.interrupts.pio = system.membus.master 74 system.cpu.interrupts.int_master = system.membus.slave 75 system.cpu.interrupts.int_slave = system.membus.master | 73 system.cpu.interrupts[0].pio = system.membus.master 74 system.cpu.interrupts[0].int_master = system.membus.slave 75 system.cpu.interrupts[0].int_slave = system.membus.master |
76 77# Create a DDR3 memory controller and connect it to the membus 78system.mem_ctrl = DDR3_1600_x64() 79system.mem_ctrl.range = system.mem_ranges[0] 80system.mem_ctrl.port = system.membus.master 81 82# Connect the system up to the membus 83system.system_port = system.membus.slave --- 24 unchanged lines hidden --- | 76 77# Create a DDR3 memory controller and connect it to the membus 78system.mem_ctrl = DDR3_1600_x64() 79system.mem_ctrl.range = system.mem_ranges[0] 80system.mem_ctrl.port = system.membus.master 81 82# Connect the system up to the membus 83system.system_port = system.membus.slave --- 24 unchanged lines hidden --- |