| se.py (9815:3b3b94536547) | se.py (9827:f47274776aa0) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154# Check -- do not allow SMT with multiple CPUs 155if options.smt and options.num_cpus > 1: 156 fatal("You cannot use SMT with multiple CPUs!") 157 158np = options.num_cpus 159system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 160 physmem = MemClass(range=AddrRange(options.mem_size)), 161 mem_mode = test_mem_mode, | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154# Check -- do not allow SMT with multiple CPUs 155if options.smt and options.num_cpus > 1: 156 fatal("You cannot use SMT with multiple CPUs!") 157 158np = options.num_cpus 159system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 160 physmem = MemClass(range=AddrRange(options.mem_size)), 161 mem_mode = test_mem_mode, |
| 162 clk_domain = SrcClockDomain(clock = options.sys_clock), | |
| 163 cache_line_size = options.cacheline_size) 164 | 162 cache_line_size = options.cacheline_size) 163 |
| 164# Create a top-level voltage domain 165system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 166 167# Create a source clock for the system and set the clock period 168system.clk_domain = SrcClockDomain(clock = options.sys_clock, 169 voltage_domain = system.voltage_domain) 170 171# Create a CPU voltage domain 172system.cpu_voltage_domain = VoltageDomain() 173 |
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| 165# Create a separate clock domain for the CPUs | 174# Create a separate clock domain for the CPUs |
| 166system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) | 175system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 176 voltage_domain = 177 system.cpu_voltage_domain) |
| 167 168# All cpus belong to a common cpu_clk_domain, therefore running at a common 169# frequency. 170for cpu in system.cpu: 171 cpu.clk_domain = system.cpu_clk_domain 172 173# Sanity check 174if options.fastmem: --- 69 unchanged lines hidden --- | 178 179# All cpus belong to a common cpu_clk_domain, therefore running at a common 180# frequency. 181for cpu in system.cpu: 182 cpu.clk_domain = system.cpu_clk_domain 183 184# Sanity check 185if options.fastmem: --- 69 unchanged lines hidden --- |