| se.py (9665:6dbdeee787cc) | se.py (9756:0b4a08751b42) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155# Check -- do not allow SMT with multiple CPUs 156if options.smt and options.num_cpus > 1: 157 fatal("You cannot use SMT with multiple CPUs!") 158 159np = options.num_cpus 160system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 161 physmem = MemClass(range=AddrRange("512MB")), | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155# Check -- do not allow SMT with multiple CPUs 156if options.smt and options.num_cpus > 1: 157 fatal("You cannot use SMT with multiple CPUs!") 158 159np = options.num_cpus 160system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 161 physmem = MemClass(range=AddrRange("512MB")), |
| 162 membus = CoherentBus(), mem_mode = test_mem_mode) | 162 mem_mode = test_mem_mode) |
| 163 164# Sanity check 165if options.fastmem: 166 if CPUClass != AtomicSimpleCPU: 167 fatal("Fastmem can only be used with atomic CPU!") 168 if (options.caches or options.l2cache): 169 fatal("You cannot use fastmem in combination with caches!") 170 --- 49 unchanged lines hidden (view full) --- 220 system.cpu[i].dcache_port = ruby_port.slave 221 if buildEnv['TARGET_ISA'] == 'x86': 222 system.cpu[i].interrupts.pio = ruby_port.master 223 system.cpu[i].interrupts.int_master = ruby_port.slave 224 system.cpu[i].interrupts.int_slave = ruby_port.master 225 system.cpu[i].itb.walker.port = ruby_port.slave 226 system.cpu[i].dtb.walker.port = ruby_port.slave 227else: | 163 164# Sanity check 165if options.fastmem: 166 if CPUClass != AtomicSimpleCPU: 167 fatal("Fastmem can only be used with atomic CPU!") 168 if (options.caches or options.l2cache): 169 fatal("You cannot use fastmem in combination with caches!") 170 --- 49 unchanged lines hidden (view full) --- 220 system.cpu[i].dcache_port = ruby_port.slave 221 if buildEnv['TARGET_ISA'] == 'x86': 222 system.cpu[i].interrupts.pio = ruby_port.master 223 system.cpu[i].interrupts.int_master = ruby_port.slave 224 system.cpu[i].interrupts.int_slave = ruby_port.master 225 system.cpu[i].itb.walker.port = ruby_port.slave 226 system.cpu[i].dtb.walker.port = ruby_port.slave 227else: |
| 228 system.membus = CoherentBus() |
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| 228 system.system_port = system.membus.slave 229 system.physmem.port = system.membus.master 230 CacheConfig.config_cache(options, system) 231 232root = Root(full_system = False, system = system) 233Simulation.run(options, root, system, FutureClass) | 229 system.system_port = system.membus.slave 230 system.physmem.port = system.membus.master 231 CacheConfig.config_cache(options, system) 232 233root = Root(full_system = False, system = system) 234Simulation.run(options, root, system, FutureClass) |