| se.py (9217:d3772fe85fa6) | se.py (9222:dfc6a4ba338c) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 184 unchanged lines hidden (view full) --- 193 system.cpu[i].createInterruptController() 194 system.cpu[i].interrupts.pio = ruby_port.master 195 system.cpu[i].interrupts.int_master = ruby_port.slave 196 system.cpu[i].interrupts.int_slave = ruby_port.master 197 198 # Connect the cpu's cache ports to Ruby 199 system.cpu[i].icache_port = ruby_port.slave 200 system.cpu[i].dcache_port = ruby_port.slave | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 184 unchanged lines hidden (view full) --- 193 system.cpu[i].createInterruptController() 194 system.cpu[i].interrupts.pio = ruby_port.master 195 system.cpu[i].interrupts.int_master = ruby_port.slave 196 system.cpu[i].interrupts.int_slave = ruby_port.master 197 198 # Connect the cpu's cache ports to Ruby 199 system.cpu[i].icache_port = ruby_port.slave 200 system.cpu[i].dcache_port = ruby_port.slave |
| 201 if buildEnv['TARGET_ISA'] == 'x86': 202 system.cpu[i].itb.walker.port = ruby_port.slave 203 system.cpu[i].dtb.walker.port = ruby_port.slave |
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| 201else: 202 system.system_port = system.membus.slave 203 system.physmem.port = system.membus.master 204 CacheConfig.config_cache(options, system) 205 206root = Root(full_system = False, system = system) 207Simulation.run(options, root, system, FutureClass) | 204else: 205 system.system_port = system.membus.slave 206 system.physmem.port = system.membus.master 207 CacheConfig.config_cache(options, system) 208 209root = Root(full_system = False, system = system) 210Simulation.run(options, root, system, FutureClass) |