| se.py (8862:dedd8be81731) | se.py (8887:20ea02da9c53) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 161 unchanged lines hidden (view full) --- 170CPUClass.numThreads = numThreads; 171 172np = options.num_cpus 173 174system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 175 physmem = PhysicalMemory(range=AddrRange("512MB")), 176 membus = Bus(), mem_mode = test_mem_mode) 177 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 161 unchanged lines hidden (view full) --- 170CPUClass.numThreads = numThreads; 171 172np = options.num_cpus 173 174system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 175 physmem = PhysicalMemory(range=AddrRange("512MB")), 176 membus = Bus(), mem_mode = test_mem_mode) 177 |
| 178if options.ruby: 179 options.use_map = True 180 Ruby.create_system(options, system) 181 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 182else: 183 system.system_port = system.membus.slave 184 system.physmem.port = system.membus.master 185 CacheConfig.config_cache(options, system) 186 | |
| 187for i in xrange(np): 188 system.cpu[i].workload = multiprocesses[i] 189 190 if options.ruby: 191 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave 192 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave 193 194 if options.fastmem: 195 system.cpu[0].physmem_port = system.physmem.port 196 | 178for i in xrange(np): 179 system.cpu[i].workload = multiprocesses[i] 180 181 if options.ruby: 182 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave 183 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave 184 185 if options.fastmem: 186 system.cpu[0].physmem_port = system.physmem.port 187 |
| 188 if options.checker: 189 system.cpu[i].addCheckerCpu() 190 191if options.ruby: 192 options.use_map = True 193 Ruby.create_system(options, system) 194 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 195else: 196 system.system_port = system.membus.slave 197 system.physmem.port = system.membus.master 198 CacheConfig.config_cache(options, system) 199 |
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| 197root = Root(full_system = False, system = system) 198 199Simulation.run(options, root, system, FutureClass) | 200root = Root(full_system = False, system = system) 201 202Simulation.run(options, root, system, FutureClass) |