| se.py (8803:f6c5785bc8fd) | se.py (8808:8af87554ad7e) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 167 unchanged lines hidden (view full) --- 176system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 177 physmem = PhysicalMemory(range=AddrRange("512MB")), 178 membus = Bus(), mem_mode = test_mem_mode) 179 180if options.ruby: 181 options.use_map = True 182 Ruby.create_system(options, system) 183 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 167 unchanged lines hidden (view full) --- 176system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 177 physmem = PhysicalMemory(range=AddrRange("512MB")), 178 membus = Bus(), mem_mode = test_mem_mode) 179 180if options.ruby: 181 options.use_map = True 182 Ruby.create_system(options, system) 183 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) |
| 184 system.system_port = system.ruby._sys_port_proxy.port | |
| 185else: 186 system.system_port = system.membus.port 187 system.physmem.port = system.membus.port 188 CacheConfig.config_cache(options, system) 189 190for i in xrange(np): 191 system.cpu[i].workload = multiprocesses[i] 192 193 if options.ruby: 194 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 195 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 196 197 if options.fastmem: 198 system.cpu[0].physmem_port = system.physmem.port 199 200root = Root(full_system = False, system = system) 201 202Simulation.run(options, root, system, FutureClass) | 184else: 185 system.system_port = system.membus.port 186 system.physmem.port = system.membus.port 187 CacheConfig.config_cache(options, system) 188 189for i in xrange(np): 190 system.cpu[i].workload = multiprocesses[i] 191 192 if options.ruby: 193 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 194 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 195 196 if options.fastmem: 197 system.cpu[0].physmem_port = system.physmem.port 198 199root = Root(full_system = False, system = system) 200 201Simulation.run(options, root, system, FutureClass) |