| se.py (8718:062bf3879857) | se.py (8732:fd510b6e124d) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 170 unchanged lines hidden (view full) --- 179system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 180 physmem = PhysicalMemory(range=AddrRange("512MB")), 181 membus = Bus(), mem_mode = test_mem_mode) 182 183if options.ruby: 184 options.use_map = True 185 Ruby.create_system(options, system) 186 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 170 unchanged lines hidden (view full) --- 179system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 180 physmem = PhysicalMemory(range=AddrRange("512MB")), 181 membus = Bus(), mem_mode = test_mem_mode) 182 183if options.ruby: 184 options.use_map = True 185 Ruby.create_system(options, system) 186 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) |
| 187 system.system_port = system.ruby._sys_port_proxy.port | |
| 188else: 189 system.system_port = system.membus.port 190 system.physmem.port = system.membus.port 191 CacheConfig.config_cache(options, system) 192 193for i in xrange(np): 194 system.cpu[i].workload = multiprocesses[i] 195 196 if options.ruby: 197 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 198 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 199 200 if options.fastmem: 201 system.cpu[0].physmem_port = system.physmem.port 202 203root = Root(system = system) 204 205Simulation.run(options, root, system, FutureClass) | 187else: 188 system.system_port = system.membus.port 189 system.physmem.port = system.membus.port 190 CacheConfig.config_cache(options, system) 191 192for i in xrange(np): 193 system.cpu[i].workload = multiprocesses[i] 194 195 if options.ruby: 196 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 197 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 198 199 if options.fastmem: 200 system.cpu[0].physmem_port = system.physmem.port 201 202root = Root(system = system) 203 204Simulation.run(options, root, system, FutureClass) |