se.py (8322:19949c6de823) | se.py (8436:5648986156db) |
---|---|
1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 163 unchanged lines hidden (view full) --- 172np = options.num_cpus 173 174system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 175 physmem = PhysicalMemory(range=AddrRange("512MB")), 176 membus = Bus(), mem_mode = test_mem_mode) 177 178if options.ruby: 179 options.use_map = True | 1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 163 unchanged lines hidden (view full) --- 172np = options.num_cpus 173 174system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 175 physmem = PhysicalMemory(range=AddrRange("512MB")), 176 membus = Bus(), mem_mode = test_mem_mode) 177 178if options.ruby: 179 options.use_map = True |
180 system.ruby = Ruby.create_system(options, system) | 180 Ruby.create_system(options, system) |
181 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 182else: 183 system.physmem.port = system.membus.port 184 CacheConfig.config_cache(options, system) 185 186for i in xrange(np): 187 system.cpu[i].workload = multiprocesses[i] 188 189 if options.ruby: 190 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 191 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 192 193 if options.fastmem: 194 system.cpu[0].physmem_port = system.physmem.port 195 196root = Root(system = system) 197 198Simulation.run(options, root, system, FutureClass) | 181 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 182else: 183 system.physmem.port = system.membus.port 184 CacheConfig.config_cache(options, system) 185 186for i in xrange(np): 187 system.cpu[i].workload = multiprocesses[i] 188 189 if options.ruby: 190 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port 191 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port 192 193 if options.fastmem: 194 system.cpu[0].physmem_port = system.physmem.port 195 196root = Root(system = system) 197 198Simulation.run(options, root, system, FutureClass) |