se.py (6654:4c84e771cca7) | se.py (6978:ab05e20dc4a7) |
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1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 137 unchanged lines hidden (view full) --- 146 147system.physmem.port = system.membus.port 148 149if options.l2cache: 150 system.l2 = L2Cache(size='2MB') 151 system.tol2bus = Bus() 152 system.l2.cpu_side = system.tol2bus.port 153 system.l2.mem_side = system.membus.port | 1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 137 unchanged lines hidden (view full) --- 146 147system.physmem.port = system.membus.port 148 149if options.l2cache: 150 system.l2 = L2Cache(size='2MB') 151 system.tol2bus = Bus() 152 system.l2.cpu_side = system.tol2bus.port 153 system.l2.mem_side = system.membus.port |
154 system.l2.num_cpus = np |
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154 155for i in xrange(np): 156 if options.caches: 157 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 158 L1Cache(size = '64kB')) 159 if options.l2cache: 160 system.cpu[i].connectMemPorts(system.tol2bus) 161 else: 162 system.cpu[i].connectMemPorts(system.membus) 163 system.cpu[i].workload = process 164 165 if options.fastmem: 166 system.cpu[0].physmem_port = system.physmem.port 167 168root = Root(system = system) 169 170Simulation.run(options, root, system, FutureClass) | 155 156for i in xrange(np): 157 if options.caches: 158 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 159 L1Cache(size = '64kB')) 160 if options.l2cache: 161 system.cpu[i].connectMemPorts(system.tol2bus) 162 else: 163 system.cpu[i].connectMemPorts(system.membus) 164 system.cpu[i].workload = process 165 166 if options.fastmem: 167 system.cpu[0].physmem_port = system.physmem.port 168 169root = Root(system = system) 170 171Simulation.run(options, root, system, FutureClass) |