se.py (4847:41126ac89de7) se.py (4968:f1c856d8c460)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 100 unchanged lines hidden (view full) ---

109 system.tol2bus = Bus()
110 system.l2.cpu_side = system.tol2bus.port
111 system.l2.mem_side = system.membus.port
112 system.cpu[i].connectMemPorts(system.tol2bus)
113 else:
114 system.cpu[i].connectMemPorts(system.membus)
115 system.cpu[i].workload = process
116
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 100 unchanged lines hidden (view full) ---

109 system.tol2bus = Bus()
110 system.l2.cpu_side = system.tol2bus.port
111 system.l2.mem_side = system.membus.port
112 system.cpu[i].connectMemPorts(system.tol2bus)
113 else:
114 system.cpu[i].connectMemPorts(system.membus)
115 system.cpu[i].workload = process
116
117 if options.fastmem:
118 system.cpu[0].physmem_port = system.physmem.port
119
117root = Root(system = system)
118
119Simulation.run(options, root, system, FutureClass)
120root = Root(system = system)
121
122Simulation.run(options, root, system, FutureClass)