| se.py (13684:076506a21535) | se.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 157 unchanged lines hidden (view full) --- 166(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 167CPUClass.numThreads = numThreads 168 169# Check -- do not allow SMT with multiple CPUs 170if options.smt and options.num_cpus > 1: 171 fatal("You cannot use SMT with multiple CPUs!") 172 173np = options.num_cpus | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 157 unchanged lines hidden (view full) --- 166(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 167CPUClass.numThreads = numThreads 168 169# Check -- do not allow SMT with multiple CPUs 170if options.smt and options.num_cpus > 1: 171 fatal("You cannot use SMT with multiple CPUs!") 172 173np = options.num_cpus |
| 174system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], | 174system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)], |
| 175 mem_mode = test_mem_mode, 176 mem_ranges = [AddrRange(options.mem_size)], 177 cache_line_size = options.cacheline_size) 178 179if numThreads > 1: 180 system.multi_thread = True 181 182# Create a top-level voltage domain --- 32 unchanged lines hidden (view full) --- 215 216# Sanity check 217if options.simpoint_profile: 218 if not CpuConfig.is_noncaching_cpu(CPUClass): 219 fatal("SimPoint/BPProbe should be done with an atomic cpu") 220 if np > 1: 221 fatal("SimPoint generation not supported with more than one CPUs") 222 | 175 mem_mode = test_mem_mode, 176 mem_ranges = [AddrRange(options.mem_size)], 177 cache_line_size = options.cacheline_size) 178 179if numThreads > 1: 180 system.multi_thread = True 181 182# Create a top-level voltage domain --- 32 unchanged lines hidden (view full) --- 215 216# Sanity check 217if options.simpoint_profile: 218 if not CpuConfig.is_noncaching_cpu(CPUClass): 219 fatal("SimPoint/BPProbe should be done with an atomic cpu") 220 if np > 1: 221 fatal("SimPoint generation not supported with more than one CPUs") 222 |
| 223for i in xrange(np): | 223for i in range(np): |
| 224 if options.smt: 225 system.cpu[i].workload = multiprocesses 226 elif len(multiprocesses) == 1: 227 system.cpu[i].workload = multiprocesses[0] 228 else: 229 system.cpu[i].workload = multiprocesses[i] 230 231 if options.simpoint_profile: --- 9 unchanged lines hidden (view full) --- 241 system.cpu[i].createThreads() 242 243if options.ruby: 244 Ruby.create_system(options, False, system) 245 assert(options.num_cpus == len(system.ruby._cpu_ports)) 246 247 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 248 voltage_domain = system.voltage_domain) | 224 if options.smt: 225 system.cpu[i].workload = multiprocesses 226 elif len(multiprocesses) == 1: 227 system.cpu[i].workload = multiprocesses[0] 228 else: 229 system.cpu[i].workload = multiprocesses[i] 230 231 if options.simpoint_profile: --- 9 unchanged lines hidden (view full) --- 241 system.cpu[i].createThreads() 242 243if options.ruby: 244 Ruby.create_system(options, False, system) 245 assert(options.num_cpus == len(system.ruby._cpu_ports)) 246 247 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 248 voltage_domain = system.voltage_domain) |
| 249 for i in xrange(np): | 249 for i in range(np): |
| 250 ruby_port = system.ruby._cpu_ports[i] 251 252 # Create the interrupt controller and connect its ports to Ruby 253 # Note that the interrupt controller is always present but only 254 # in x86 does it have message ports that need to be connected 255 system.cpu[i].createInterruptController() 256 257 # Connect the cpu's cache ports to Ruby --- 17 unchanged lines hidden --- | 250 ruby_port = system.ruby._cpu_ports[i] 251 252 # Create the interrupt controller and connect its ports to Ruby 253 # Note that the interrupt controller is always present but only 254 # in x86 does it have message ports that need to be connected 255 system.cpu[i].createInterruptController() 256 257 # Connect the cpu's cache ports to Ruby --- 17 unchanged lines hidden --- |