Cross Reference: /gem5/configs/example/se.py

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se.py (11147:cc8d6e99cf46)	se.py (11150:a8a64cca231b)
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 251 unchanged lines hidden (view full) --- 260 # Note that the interrupt controller is always present but only 261 # in x86 does it have message ports that need to be connected 262 system.cpu[i].createInterruptController() 263 264 # Connect the cpu's cache ports to Ruby 265 system.cpu[i].icache_port = ruby_port.slave 266 system.cpu[i].dcache_port = ruby_port.slave 267 if buildEnv['TARGET_ISA'] == 'x86':	1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 251 unchanged lines hidden (view full) --- 260 # Note that the interrupt controller is always present but only 261 # in x86 does it have message ports that need to be connected 262 system.cpu[i].createInterruptController() 263 264 # Connect the cpu's cache ports to Ruby 265 system.cpu[i].icache_port = ruby_port.slave 266 system.cpu[i].dcache_port = ruby_port.slave 267 if buildEnv['TARGET_ISA'] == 'x86':
268 system.cpu[i].interrupts.pio = ruby_port.master 269 system.cpu[i].interrupts.int_master = ruby_port.slave 270 system.cpu[i].interrupts.int_slave = ruby_port.master	268 system.cpu[i].interrupts[0].pio = ruby_port.master 269 system.cpu[i].interrupts[0].int_master = ruby_port.slave 270 system.cpu[i].interrupts[0].int_slave = ruby_port.master
271 system.cpu[i].itb.walker.port = ruby_port.slave 272 system.cpu[i].dtb.walker.port = ruby_port.slave 273else: 274 MemClass = Simulation.setMemClass(options) 275 system.membus = SystemXBar() 276 system.system_port = system.membus.slave 277 CacheConfig.config_cache(options, system) 278 MemConfig.config_mem(options, system) 279 280root = Root(full_system = False, system = system) 281Simulation.run(options, root, system, FutureClass)	271 system.cpu[i].itb.walker.port = ruby_port.slave 272 system.cpu[i].dtb.walker.port = ruby_port.slave 273else: 274 MemClass = Simulation.setMemClass(options) 275 system.membus = SystemXBar() 276 system.system_port = system.membus.slave 277 CacheConfig.config_cache(options, system) 278 MemConfig.config_mem(options, system) 279 280root = Root(full_system = False, system = system) 281Simulation.run(options, root, system, FutureClass)