| se.py (10650:a6fe75e8296b) | se.py (10720:67b3e74de9ae) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 251 unchanged lines hidden (view full) --- 260 if buildEnv['TARGET_ISA'] == 'x86': 261 system.cpu[i].interrupts.pio = ruby_port.master 262 system.cpu[i].interrupts.int_master = ruby_port.slave 263 system.cpu[i].interrupts.int_slave = ruby_port.master 264 system.cpu[i].itb.walker.port = ruby_port.slave 265 system.cpu[i].dtb.walker.port = ruby_port.slave 266else: 267 MemClass = Simulation.setMemClass(options) | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 251 unchanged lines hidden (view full) --- 260 if buildEnv['TARGET_ISA'] == 'x86': 261 system.cpu[i].interrupts.pio = ruby_port.master 262 system.cpu[i].interrupts.int_master = ruby_port.slave 263 system.cpu[i].interrupts.int_slave = ruby_port.master 264 system.cpu[i].itb.walker.port = ruby_port.slave 265 system.cpu[i].dtb.walker.port = ruby_port.slave 266else: 267 MemClass = Simulation.setMemClass(options) |
| 268 system.membus = CoherentXBar() | 268 system.membus = SystemXBar() |
| 269 system.system_port = system.membus.slave 270 CacheConfig.config_cache(options, system) 271 MemConfig.config_mem(options, system) 272 273root = Root(full_system = False, system = system) 274Simulation.run(options, root, system, FutureClass) | 269 system.system_port = system.membus.slave 270 CacheConfig.config_cache(options, system) 271 MemConfig.config_mem(options, system) 272 273root = Root(full_system = False, system = system) 274Simulation.run(options, root, system, FutureClass) |