| se.py (10405:7a618c07e663) | se.py (10519:7a3ad4b09ce4) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226 sys.exit(1) 227 228 # Use SimpleMemory with the null option since this memory is only used 229 # for determining which addresses are within the range of the memory. 230 # No space allocation is required. 231 system.physmem = SimpleMemory(range=AddrRange(options.mem_size), 232 null = True) 233 options.use_map = True | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226 sys.exit(1) 227 228 # Use SimpleMemory with the null option since this memory is only used 229 # for determining which addresses are within the range of the memory. 230 # No space allocation is required. 231 system.physmem = SimpleMemory(range=AddrRange(options.mem_size), 232 null = True) 233 options.use_map = True |
| 234 Ruby.create_system(options, system) | 234 Ruby.create_system(options, False, system) |
| 235 assert(options.num_cpus == len(system.ruby._cpu_ports)) 236 237 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 238 voltage_domain = system.voltage_domain) 239 for i in xrange(np): 240 ruby_port = system.ruby._cpu_ports[i] 241 242 # Create the interrupt controller and connect its ports to Ruby --- 22 unchanged lines hidden --- | 235 assert(options.num_cpus == len(system.ruby._cpu_ports)) 236 237 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 238 voltage_domain = system.voltage_domain) 239 for i in xrange(np): 240 ruby_port = system.ruby._cpu_ports[i] 241 242 # Create the interrupt controller and connect its ports to Ruby --- 22 unchanged lines hidden --- |