| se.py (10150:240969297314) | se.py (10300:ed3816dae6d5) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 # for determining which addresses are within the range of the memory. 231 # No space allocation is required. 232 system.physmem = SimpleMemory(range=AddrRange(options.mem_size), 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) 236 assert(options.num_cpus == len(system.ruby._cpu_ports)) 237 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 # for determining which addresses are within the range of the memory. 231 # No space allocation is required. 232 system.physmem = SimpleMemory(range=AddrRange(options.mem_size), 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) 236 assert(options.num_cpus == len(system.ruby._cpu_ports)) 237 |
| 238 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 239 voltage_domain = system.voltage_domain) |
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| 238 for i in xrange(np): 239 ruby_port = system.ruby._cpu_ports[i] 240 241 # Create the interrupt controller and connect its ports to Ruby 242 # Note that the interrupt controller is always present but only 243 # in x86 does it have message ports that need to be connected 244 system.cpu[i].createInterruptController() 245 --- 18 unchanged lines hidden --- | 240 for i in xrange(np): 241 ruby_port = system.ruby._cpu_ports[i] 242 243 # Create the interrupt controller and connect its ports to Ruby 244 # Note that the interrupt controller is always present but only 245 # in x86 does it have message ports that need to be connected 246 system.cpu[i].createInterruptController() 247 --- 18 unchanged lines hidden --- |