| se.py (10120:f5ceb3c3edb6) | se.py (10150:240969297314) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 143 unchanged lines hidden (view full) --- 152else: 153 print >> sys.stderr, "No workload specified. Exiting!\n" 154 sys.exit(1) 155 156 157(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 158CPUClass.numThreads = numThreads 159 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 143 unchanged lines hidden (view full) --- 152else: 153 print >> sys.stderr, "No workload specified. Exiting!\n" 154 sys.exit(1) 155 156 157(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 158CPUClass.numThreads = numThreads 159 |
| 160MemClass = Simulation.setMemClass(options) 161 | |
| 162# Check -- do not allow SMT with multiple CPUs 163if options.smt and options.num_cpus > 1: 164 fatal("You cannot use SMT with multiple CPUs!") 165 166np = options.num_cpus 167system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 168 mem_mode = test_mem_mode, 169 mem_ranges = [AddrRange(options.mem_size)], --- 53 unchanged lines hidden (view full) --- 223 224 system.cpu[i].createThreads() 225 226if options.ruby: 227 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 229 sys.exit(1) 230 | 160# Check -- do not allow SMT with multiple CPUs 161if options.smt and options.num_cpus > 1: 162 fatal("You cannot use SMT with multiple CPUs!") 163 164np = options.num_cpus 165system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 166 mem_mode = test_mem_mode, 167 mem_ranges = [AddrRange(options.mem_size)], --- 53 unchanged lines hidden (view full) --- 221 222 system.cpu[i].createThreads() 223 224if options.ruby: 225 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 226 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 227 sys.exit(1) 228 |
| 231 # Set the option for physmem so that it is not allocated any space 232 system.physmem = MemClass(range=AddrRange(options.mem_size), | 229 # Use SimpleMemory with the null option since this memory is only used 230 # for determining which addresses are within the range of the memory. 231 # No space allocation is required. 232 system.physmem = SimpleMemory(range=AddrRange(options.mem_size), |
| 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) 236 assert(options.num_cpus == len(system.ruby._cpu_ports)) 237 238 for i in xrange(np): 239 ruby_port = system.ruby._cpu_ports[i] 240 --- 7 unchanged lines hidden (view full) --- 248 system.cpu[i].dcache_port = ruby_port.slave 249 if buildEnv['TARGET_ISA'] == 'x86': 250 system.cpu[i].interrupts.pio = ruby_port.master 251 system.cpu[i].interrupts.int_master = ruby_port.slave 252 system.cpu[i].interrupts.int_slave = ruby_port.master 253 system.cpu[i].itb.walker.port = ruby_port.slave 254 system.cpu[i].dtb.walker.port = ruby_port.slave 255else: | 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) 236 assert(options.num_cpus == len(system.ruby._cpu_ports)) 237 238 for i in xrange(np): 239 ruby_port = system.ruby._cpu_ports[i] 240 --- 7 unchanged lines hidden (view full) --- 248 system.cpu[i].dcache_port = ruby_port.slave 249 if buildEnv['TARGET_ISA'] == 'x86': 250 system.cpu[i].interrupts.pio = ruby_port.master 251 system.cpu[i].interrupts.int_master = ruby_port.slave 252 system.cpu[i].interrupts.int_slave = ruby_port.master 253 system.cpu[i].itb.walker.port = ruby_port.slave 254 system.cpu[i].dtb.walker.port = ruby_port.slave 255else: |
| 256 MemClass = Simulation.setMemClass(options) |
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| 256 system.membus = CoherentBus() 257 system.system_port = system.membus.slave 258 CacheConfig.config_cache(options, system) 259 MemConfig.config_mem(options, system) 260 261root = Root(full_system = False, system = system) 262Simulation.run(options, root, system, FutureClass) | 257 system.membus = CoherentBus() 258 system.system_port = system.membus.slave 259 CacheConfig.config_cache(options, system) 260 MemConfig.config_mem(options, system) 261 262root = Root(full_system = False, system = system) 263Simulation.run(options, root, system, FutureClass) |