se.py (10118:5e1f04b4d5e4) | se.py (10120:f5ceb3c3edb6) |
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1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 219 unchanged lines hidden (view full) --- 228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 229 sys.exit(1) 230 231 # Set the option for physmem so that it is not allocated any space 232 system.physmem = MemClass(range=AddrRange(options.mem_size), 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 219 unchanged lines hidden (view full) --- 228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 229 sys.exit(1) 230 231 # Set the option for physmem so that it is not allocated any space 232 system.physmem = MemClass(range=AddrRange(options.mem_size), 233 null = True) 234 options.use_map = True 235 Ruby.create_system(options, system) |
236 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) | 236 assert(options.num_cpus == len(system.ruby._cpu_ports)) |
237 238 for i in xrange(np): | 237 238 for i in xrange(np): |
239 ruby_port = system.ruby._cpu_ruby_ports[i] | 239 ruby_port = system.ruby._cpu_ports[i] |
240 241 # Create the interrupt controller and connect its ports to Ruby 242 # Note that the interrupt controller is always present but only 243 # in x86 does it have message ports that need to be connected 244 system.cpu[i].createInterruptController() 245 246 # Connect the cpu's cache ports to Ruby 247 system.cpu[i].icache_port = ruby_port.slave --- 15 unchanged lines hidden --- | 240 241 # Create the interrupt controller and connect its ports to Ruby 242 # Note that the interrupt controller is always present but only 243 # in x86 does it have message ports that need to be connected 244 system.cpu[i].createInterruptController() 245 246 # Connect the cpu's cache ports to Ruby 247 system.cpu[i].icache_port = ruby_port.slave --- 15 unchanged lines hidden --- |