| se.py (10037:5cac77888310) | se.py (10092:c0db268f811b) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226if options.ruby: 227 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 229 sys.exit(1) 230 231 # Set the option for physmem so that it is not allocated any space 232 system.physmem = MemClass(range=AddrRange(options.mem_size), 233 null = True) | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226if options.ruby: 227 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 229 sys.exit(1) 230 231 # Set the option for physmem so that it is not allocated any space 232 system.physmem = MemClass(range=AddrRange(options.mem_size), 233 null = True) |
| 234 | |
| 235 options.use_map = True | 234 options.use_map = True |
| 236 Ruby.create_system(options, system) | 235 236 system.piobus = NoncoherentBus() 237 Ruby.create_system(options, system, system.piobus) |
| 237 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 238 239 for i in xrange(np): 240 ruby_port = system.ruby._cpu_ruby_ports[i] 241 242 # Create the interrupt controller and connect its ports to Ruby 243 # Note that the interrupt controller is always present but only 244 # in x86 does it have message ports that need to be connected --- 19 unchanged lines hidden --- | 238 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 239 240 for i in xrange(np): 241 ruby_port = system.ruby._cpu_ruby_ports[i] 242 243 # Create the interrupt controller and connect its ports to Ruby 244 # Note that the interrupt controller is always present but only 245 # in x86 does it have message ports that need to be connected --- 19 unchanged lines hidden --- |