1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Steve Reinhardt 40 41# Simple test script 42# 43# "m5 test.py" 44 45from __future__ import print_function 46from __future__ import absolute_import 47 48import optparse 49import sys 50import os 51 52import m5 53from m5.defines import buildEnv 54from m5.objects import * 55from m5.util import addToPath, fatal, warn 56 57addToPath('../') 58 59from ruby import Ruby 60 61from common import Options 62from common import Simulation 63from common import CacheConfig 64from common import CpuConfig 65from common import BPConfig 66from common import MemConfig
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67from common.FileSystemConfig import redirect_paths, config_filesystem
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67from common.FileSystemConfig import config_filesystem |
68from common.Caches import * 69from common.cpu2000 import * 70 71def get_processes(options): 72 """Interprets provided options and returns a list of processes""" 73 74 multiprocesses = [] 75 inputs = [] 76 outputs = [] 77 errouts = [] 78 pargs = [] 79 80 workloads = options.cmd.split(';') 81 if options.input != "": 82 inputs = options.input.split(';') 83 if options.output != "": 84 outputs = options.output.split(';') 85 if options.errout != "": 86 errouts = options.errout.split(';') 87 if options.options != "": 88 pargs = options.options.split(';') 89 90 idx = 0 91 for wrkld in workloads: 92 process = Process(pid = 100 + idx) 93 process.executable = wrkld 94 process.cwd = os.getcwd() 95 96 if options.env: 97 with open(options.env, 'r') as f: 98 process.env = [line.rstrip() for line in f] 99 100 if len(pargs) > idx: 101 process.cmd = [wrkld] + pargs[idx].split() 102 else: 103 process.cmd = [wrkld] 104 105 if len(inputs) > idx: 106 process.input = inputs[idx] 107 if len(outputs) > idx: 108 process.output = outputs[idx] 109 if len(errouts) > idx: 110 process.errout = errouts[idx] 111 112 multiprocesses.append(process) 113 idx += 1 114 115 if options.smt: 116 assert(options.cpu_type == "DerivO3CPU") 117 return multiprocesses, idx 118 else: 119 return multiprocesses, 1 120 121 122parser = optparse.OptionParser() 123Options.addCommonOptions(parser) 124Options.addSEOptions(parser) 125 126if '--ruby' in sys.argv: 127 Ruby.define_options(parser) 128 129(options, args) = parser.parse_args() 130 131if args: 132 print("Error: script doesn't take any positional arguments") 133 sys.exit(1) 134 135multiprocesses = [] 136numThreads = 1 137 138if options.bench: 139 apps = options.bench.split("-") 140 if len(apps) != options.num_cpus: 141 print("number of benchmarks not equal to set num_cpus!") 142 sys.exit(1) 143 144 for app in apps: 145 try: 146 if buildEnv['TARGET_ISA'] == 'alpha': 147 exec("workload = %s('alpha', 'tru64', '%s')" % ( 148 app, options.spec_input)) 149 elif buildEnv['TARGET_ISA'] == 'arm': 150 exec("workload = %s('arm_%s', 'linux', '%s')" % ( 151 app, options.arm_iset, options.spec_input)) 152 else: 153 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 154 app, options.spec_input)) 155 multiprocesses.append(workload.makeProcess()) 156 except: 157 print("Unable to find workload for %s: %s" % 158 (buildEnv['TARGET_ISA'], app), 159 file=sys.stderr) 160 sys.exit(1) 161elif options.cmd: 162 multiprocesses, numThreads = get_processes(options) 163else: 164 print("No workload specified. Exiting!\n", file=sys.stderr) 165 sys.exit(1) 166 167 168(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 169CPUClass.numThreads = numThreads 170 171# Check -- do not allow SMT with multiple CPUs 172if options.smt and options.num_cpus > 1: 173 fatal("You cannot use SMT with multiple CPUs!") 174 175np = options.num_cpus 176system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)], 177 mem_mode = test_mem_mode, 178 mem_ranges = [AddrRange(options.mem_size)], 179 cache_line_size = options.cacheline_size) 180 181if numThreads > 1: 182 system.multi_thread = True 183 184# Create a top-level voltage domain 185system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 186 187# Create a source clock for the system and set the clock period 188system.clk_domain = SrcClockDomain(clock = options.sys_clock, 189 voltage_domain = system.voltage_domain) 190 191# Create a CPU voltage domain 192system.cpu_voltage_domain = VoltageDomain() 193 194# Create a separate clock domain for the CPUs 195system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 196 voltage_domain = 197 system.cpu_voltage_domain) 198 199# If elastic tracing is enabled, then configure the cpu and attach the elastic 200# trace probe 201if options.elastic_trace_en: 202 CpuConfig.config_etrace(CPUClass, system.cpu, options) 203 204# All cpus belong to a common cpu_clk_domain, therefore running at a common 205# frequency. 206for cpu in system.cpu: 207 cpu.clk_domain = system.cpu_clk_domain 208 209if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 210 if buildEnv['TARGET_ISA'] == 'x86': 211 system.kvm_vm = KvmVM() 212 for process in multiprocesses: 213 process.useArchPT = True 214 process.kvmInSE = True 215 else: 216 fatal("KvmCPU can only be used in SE mode with x86") 217 218# Sanity check 219if options.simpoint_profile: 220 if not CpuConfig.is_noncaching_cpu(CPUClass): 221 fatal("SimPoint/BPProbe should be done with an atomic cpu") 222 if np > 1: 223 fatal("SimPoint generation not supported with more than one CPUs") 224 225for i in range(np): 226 if options.smt: 227 system.cpu[i].workload = multiprocesses 228 elif len(multiprocesses) == 1: 229 system.cpu[i].workload = multiprocesses[0] 230 else: 231 system.cpu[i].workload = multiprocesses[i] 232 233 if options.simpoint_profile: 234 system.cpu[i].addSimPointProbe(options.simpoint_interval) 235 236 if options.checker: 237 system.cpu[i].addCheckerCpu() 238 239 if options.bp_type: 240 bpClass = BPConfig.get(options.bp_type) 241 system.cpu[i].branchPred = bpClass() 242 243 if options.indirect_bp_type: 244 indirectBPClass = BPConfig.get_indirect(options.indirect_bp_type) 245 system.cpu[i].branchPred.indirectBranchPred = indirectBPClass() 246 247 system.cpu[i].createThreads() 248
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249system.redirect_paths = redirect_paths(os.path.expanduser(options.chroot))
250config_filesystem(options)
251
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249if options.ruby: 250 Ruby.create_system(options, False, system) 251 assert(options.num_cpus == len(system.ruby._cpu_ports)) 252 253 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 254 voltage_domain = system.voltage_domain) 255 for i in range(np): 256 ruby_port = system.ruby._cpu_ports[i] 257 258 # Create the interrupt controller and connect its ports to Ruby 259 # Note that the interrupt controller is always present but only 260 # in x86 does it have message ports that need to be connected 261 system.cpu[i].createInterruptController() 262 263 # Connect the cpu's cache ports to Ruby 264 system.cpu[i].icache_port = ruby_port.slave 265 system.cpu[i].dcache_port = ruby_port.slave 266 if buildEnv['TARGET_ISA'] == 'x86': 267 system.cpu[i].interrupts[0].pio = ruby_port.master 268 system.cpu[i].interrupts[0].int_master = ruby_port.slave 269 system.cpu[i].interrupts[0].int_slave = ruby_port.master 270 system.cpu[i].itb.walker.port = ruby_port.slave 271 system.cpu[i].dtb.walker.port = ruby_port.slave 272else: 273 MemClass = Simulation.setMemClass(options) 274 system.membus = SystemXBar() 275 system.system_port = system.membus.slave 276 CacheConfig.config_cache(options, system) 277 MemConfig.config_mem(options, system)
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278 config_filesystem(system, options) |
279 280root = Root(full_system = False, system = system) 281Simulation.run(options, root, system, FutureClass)
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