1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 133 unchanged lines hidden (view full) --- 142 smt_process.output = outputs[smt_idx] 143 if errouts and errouts[smt_idx]: 144 smt_process.errout = errouts[smt_idx] 145 process += [smt_process, ] 146 smt_idx += 1 147 numThreads = len(workloads) 148 149(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) |
150CPUClass.clock = options.clock |
151CPUClass.numThreads = numThreads; 152 153np = options.num_cpus 154 155system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 156 physmem = SimpleMemory(range=AddrRange("512MB")), 157 membus = CoherentBus(), mem_mode = test_mem_mode) 158 --- 44 unchanged lines hidden --- |