1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 146 unchanged lines hidden (view full) --- 155 if outputs and outputs[smt_idx]: 156 smt_process.output = outputs[smt_idx] 157 if errouts and errouts[smt_idx]: 158 smt_process.errout = errouts[smt_idx] 159 process += [smt_process, ] 160 smt_idx += 1 161 numThreads = len(workloads) 162 |
163(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 164CPUClass.clock = '2GHz' 165CPUClass.numThreads = numThreads; 166 167np = options.num_cpus 168 169system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 170 physmem = PhysicalMemory(range=AddrRange("512MB")), 171 membus = Bus(), mem_mode = test_mem_mode) 172 173for i in xrange(np): 174 system.cpu[i].workload = multiprocesses[i] 175 |
176 if options.fastmem: 177 system.cpu[0].physmem_port = system.physmem.port 178 179 if options.checker: 180 system.cpu[i].addCheckerCpu() 181 182if options.ruby: |
183 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 184 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 185 sys.exit(1) 186 |
187 options.use_map = True 188 Ruby.create_system(options, system) 189 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) |
190 191 for i in xrange(np): 192 ruby_port = system.ruby._cpu_ruby_ports[i] 193 194 # Create the interrupt controller and connect its ports to Ruby 195 system.cpu[i].createInterruptController() 196 system.cpu[i].interrupts.pio = ruby_port.master 197 system.cpu[i].interrupts.int_master = ruby_port.slave 198 system.cpu[i].interrupts.int_slave = ruby_port.master 199 200 # Connect the cpu's cache ports to Ruby 201 system.cpu[i].icache_port = ruby_port.slave 202 system.cpu[i].dcache_port = ruby_port.slave |
203else: 204 system.system_port = system.membus.slave 205 system.physmem.port = system.membus.master 206 CacheConfig.config_cache(options, system) 207 208root = Root(full_system = False, system = system) |
209Simulation.run(options, root, system, FutureClass) |