1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 176 unchanged lines hidden (view full) --- 185 system.system_port = system.membus.slave 186 system.physmem.port = system.membus.master 187 CacheConfig.config_cache(options, system) 188 189for i in xrange(np): 190 system.cpu[i].workload = multiprocesses[i] 191 192 if options.ruby: |
193 system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave 194 system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave |
195 196 if options.fastmem: 197 system.cpu[0].physmem_port = system.physmem.port 198 199root = Root(full_system = False, system = system) 200 201Simulation.run(options, root, system, FutureClass) |