1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 110 unchanged lines hidden (view full) --- 119 if errouts and errouts[smt_idx]: 120 smt_process.errout = errouts[smt_idx] 121 process += [smt_process, ] 122 smt_idx += 1 123 124(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 125 126CPUClass.clock = '2GHz' |
127CPUClass.numThreads = len(workloads) |
128 129np = options.num_cpus 130 131system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 132 physmem = PhysicalMemory(range=AddrRange("512MB")), 133 membus = Bus(), mem_mode = test_mem_mode) 134 135system.physmem.port = system.membus.port --- 23 unchanged lines hidden --- |