1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 86 unchanged lines hidden (view full) --- 95np = options.num_cpus 96 97system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 98 physmem = PhysicalMemory(range=AddrRange("512MB")), 99 membus = Bus(), mem_mode = test_mem_mode) 100 101system.physmem.port = system.membus.port 102 |
103if options.l2cache: 104 system.l2 = L2Cache(size='2MB') 105 system.tol2bus = Bus() 106 system.l2.cpu_side = system.tol2bus.port 107 system.l2.mem_side = system.membus.port 108 |
109for i in xrange(np): 110 if options.caches: 111 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 112 L1Cache(size = '64kB')) 113 if options.l2cache: |
114 system.cpu[i].connectMemPorts(system.tol2bus) 115 else: 116 system.cpu[i].connectMemPorts(system.membus) 117 system.cpu[i].workload = process 118 119 if options.fastmem: 120 system.cpu[0].physmem_port = system.physmem.port 121 122root = Root(system = system) 123 124Simulation.run(options, root, system, FutureClass) |