1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34from m5.objects import *
35import os, optparse, sys
36m5.AddToPath('../common')
37
38parser = optparse.OptionParser()
39
40# Benchmark options
41parser.add_option("-c", "--cmd",
42 default="../../tests/test-progs/hello/bin/alpha/linux/hello",
42 default="../tests/test-progs/hello/bin/alpha/linux/hello",
43 help="The binary to run in syscall emulation mode.")
44parser.add_option("-o", "--options", default="",
45 help="The options to pass to the binary, use \" \" around the entire\
46 string.")
47parser.add_option("-i", "--input", default="",
48 help="A file of input to give to the binary.")
49
50# System options

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124 cpu = AtomicSimpleCPU()
125
126cpu.workload = process
127cpu.cpu_id = 0
128
129system = System(cpu = cpu,
130 physmem = PhysicalMemory(range=AddrRange("512MB")),
131 membus = Bus())
132
132system.physmem.port = system.membus.port
133system.cpu.connectMemPorts(system.membus)
134system.cpu.clock = '2GHz'
135if options.caches and not options.standard_switch:
136 system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
137 MyCache(size = '64kB'))
138
137system.physmem.port = system.membus.port
138system.cpu.connectMemPorts(system.membus)
139system.cpu.mem = system.physmem
140system.cpu.clock = '2GHz'
139root = Root(system = system)
140
141if options.timing or options.detailed:
142 root.system.mem_mode = 'timing'
143
144if options.standard_switch:
145 switch_cpu = TimingSimpleCPU(defer_registration=True, cpu_id=1)
146 switch_cpu1 = DerivO3CPU(defer_registration=True, cpu_id=2)
147 switch_cpu.system = system
148 switch_cpu1.system = system
149 switch_cpu.clock = cpu.clock
150 switch_cpu1.clock = cpu.clock
151 if options.caches:
152 switch_cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
153 MyCache(size = '64kB'))
154
155 switch_cpu.workload = process
156 switch_cpu1.workload = process
159 switch_cpu.mem = system.physmem
160 switch_cpu1.mem = system.physmem
157 switch_cpu.connectMemPorts(system.membus)
158 root.switch_cpu = switch_cpu
159 root.switch_cpu1 = switch_cpu1
160 switch_cpu_list = [(system.cpu, switch_cpu)]
161 switch_cpu_list1 = [(switch_cpu, switch_cpu1)]
162
163# instantiate configuration
164m5.instantiate(root)
165
166if options.checkpoint_dir:
167 cptdir = options.checkpoint_dir
168else:
173 cptdir = os.getcwd()
169 cptdir = getcwd()
170
171if options.checkpoint_restore:
172 from os.path import isdir
173 from os import listdir, getcwd
174 import re
175
176 if not isdir(cptdir):
177 m5.panic("checkpoint dir %s does not exist!" % cptdir)

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