1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 83 unchanged lines hidden (view full) --- 92 93cpu.workload = process 94 95system = System(cpu = cpu, 96 physmem = PhysicalMemory(), 97 membus = Bus()) 98system.physmem.port = system.membus.port 99system.cpu.connectMemPorts(system.membus) |
100system.cpu.mem = system.physmem |
101 102root = Root(system = system) 103 104if options.timing or options.detailed: 105 root.system.mem_mode = 'timing' 106 107# instantiate configuration 108m5.instantiate(root) 109 110# simulate until program terminates 111if options.maxtick: 112 exit_event = m5.simulate(options.maxtick) 113else: 114 exit_event = m5.simulate() 115 116print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 117 |