102a103,108
> if options.l2cache:
> system.l2 = L2Cache(size='2MB')
> system.tol2bus = Bus()
> system.l2.cpu_side = system.tol2bus.port
> system.l2.mem_side = system.membus.port
>
108,111d113
< system.l2 = L2Cache(size='2MB')
< system.tol2bus = Bus()
< system.l2.cpu_side = system.tol2bus.port
< system.l2.mem_side = system.membus.port