1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56addToPath('../topologies')
57
58import Options
59import Ruby
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64from cpu2000 import *
65
66def get_processes(options):
67 """Interprets provided options and returns a list of processes"""
68
69 multiprocesses = []
70 inputs = []
71 outputs = []
72 errouts = []
73 pargs = []
74
75 workloads = options.cmd.split(';')
76 if options.input != "":
77 inputs = options.input.split(';')
78 if options.output != "":
79 outputs = options.output.split(';')
80 if options.errout != "":
81 errouts = options.errout.split(';')
82 if options.options != "":
83 pargs = options.options.split(';')
84
85 idx = 0
86 for wrkld in workloads:
87 process = LiveProcess()
88 process.executable = wrkld
89 process.cwd = os.getcwd()
90
91 if len(pargs) > idx:
92 process.cmd = [wrkld] + pargs[idx].split()
93 else:
94 process.cmd = [wrkld]
95
96 if len(inputs) > idx:
97 process.input = inputs[idx]
98 if len(outputs) > idx:
99 process.output = outputs[idx]
100 if len(errouts) > idx:
101 process.errout = errouts[idx]
102
103 multiprocesses.append(process)
104 idx += 1
105
106 if options.smt:
107 assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
108 return multiprocesses, idx
109 else:
110 return multiprocesses, 1
111
112
113parser = optparse.OptionParser()
114Options.addCommonOptions(parser)
115Options.addSEOptions(parser)
116
117if '--ruby' in sys.argv:
118 Ruby.define_options(parser)
119
120(options, args) = parser.parse_args()
121
122if args:
123 print "Error: script doesn't take any positional arguments"
124 sys.exit(1)
125
126multiprocesses = []
127numThreads = 1
128
129if options.bench:
130 apps = options.bench.split("-")
131 if len(apps) != options.num_cpus:
132 print "number of benchmarks not equal to set num_cpus!"
133 sys.exit(1)
134
135 for app in apps:
136 try:
137 if buildEnv['TARGET_ISA'] == 'alpha':
| 1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../common')
55addToPath('../ruby')
56addToPath('../topologies')
57
58import Options
59import Ruby
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64from cpu2000 import *
65
66def get_processes(options):
67 """Interprets provided options and returns a list of processes"""
68
69 multiprocesses = []
70 inputs = []
71 outputs = []
72 errouts = []
73 pargs = []
74
75 workloads = options.cmd.split(';')
76 if options.input != "":
77 inputs = options.input.split(';')
78 if options.output != "":
79 outputs = options.output.split(';')
80 if options.errout != "":
81 errouts = options.errout.split(';')
82 if options.options != "":
83 pargs = options.options.split(';')
84
85 idx = 0
86 for wrkld in workloads:
87 process = LiveProcess()
88 process.executable = wrkld
89 process.cwd = os.getcwd()
90
91 if len(pargs) > idx:
92 process.cmd = [wrkld] + pargs[idx].split()
93 else:
94 process.cmd = [wrkld]
95
96 if len(inputs) > idx:
97 process.input = inputs[idx]
98 if len(outputs) > idx:
99 process.output = outputs[idx]
100 if len(errouts) > idx:
101 process.errout = errouts[idx]
102
103 multiprocesses.append(process)
104 idx += 1
105
106 if options.smt:
107 assert(options.cpu_type == "detailed" or options.cpu_type == "inorder")
108 return multiprocesses, idx
109 else:
110 return multiprocesses, 1
111
112
113parser = optparse.OptionParser()
114Options.addCommonOptions(parser)
115Options.addSEOptions(parser)
116
117if '--ruby' in sys.argv:
118 Ruby.define_options(parser)
119
120(options, args) = parser.parse_args()
121
122if args:
123 print "Error: script doesn't take any positional arguments"
124 sys.exit(1)
125
126multiprocesses = []
127numThreads = 1
128
129if options.bench:
130 apps = options.bench.split("-")
131 if len(apps) != options.num_cpus:
132 print "number of benchmarks not equal to set num_cpus!"
133 sys.exit(1)
134
135 for app in apps:
136 try:
137 if buildEnv['TARGET_ISA'] == 'alpha':
|
138 exec("workload = %s('alpha', 'tru64', 'ref')" % app)
| 138 exec("workload = %s('alpha', 'tru64', '%s')" % (
139 app, options.spec_input))
140 elif buildEnv['TARGET_ISA'] == 'arm':
141 exec("workload = %s('arm_%s', 'linux', '%s')" % (
142 app, options.arm_iset, options.spec_input))
|
139 else:
| 143 else:
|
140 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
| 144 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
145 app, options.spec_input))
|
141 multiprocesses.append(workload.makeLiveProcess())
142 except:
143 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
144 sys.exit(1)
145elif options.cmd:
146 multiprocesses, numThreads = get_processes(options)
147else:
148 print >> sys.stderr, "No workload specified. Exiting!\n"
149 sys.exit(1)
150
151
152(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
153CPUClass.numThreads = numThreads
154
155MemClass = Simulation.setMemClass(options)
156
157# Check -- do not allow SMT with multiple CPUs
158if options.smt and options.num_cpus > 1:
159 fatal("You cannot use SMT with multiple CPUs!")
160
161np = options.num_cpus
162system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
163 mem_mode = test_mem_mode,
164 mem_ranges = [AddrRange(options.mem_size)],
165 cache_line_size = options.cacheline_size)
166
167# Create a top-level voltage domain
168system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
169
170# Create a source clock for the system and set the clock period
171system.clk_domain = SrcClockDomain(clock = options.sys_clock,
172 voltage_domain = system.voltage_domain)
173
174# Create a CPU voltage domain
175system.cpu_voltage_domain = VoltageDomain()
176
177# Create a separate clock domain for the CPUs
178system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
179 voltage_domain =
180 system.cpu_voltage_domain)
181
182# All cpus belong to a common cpu_clk_domain, therefore running at a common
183# frequency.
184for cpu in system.cpu:
185 cpu.clk_domain = system.cpu_clk_domain
186
187# Sanity check
188if options.fastmem:
189 if CPUClass != AtomicSimpleCPU:
190 fatal("Fastmem can only be used with atomic CPU!")
191 if (options.caches or options.l2cache):
192 fatal("You cannot use fastmem in combination with caches!")
193
194if options.simpoint_profile:
195 if not options.fastmem:
196 # Atomic CPU checked with fastmem option already
197 fatal("SimPoint generation should be done with atomic cpu and fastmem")
198 if np > 1:
199 fatal("SimPoint generation not supported with more than one CPUs")
200
201for i in xrange(np):
202 if options.smt:
203 system.cpu[i].workload = multiprocesses
204 elif len(multiprocesses) == 1:
205 system.cpu[i].workload = multiprocesses[0]
206 else:
207 system.cpu[i].workload = multiprocesses[i]
208
209 if options.fastmem:
210 system.cpu[i].fastmem = True
211
212 if options.simpoint_profile:
213 system.cpu[i].simpoint_profile = True
214 system.cpu[i].simpoint_interval = options.simpoint_interval
215
216 if options.checker:
217 system.cpu[i].addCheckerCpu()
218
219 system.cpu[i].createThreads()
220
221if options.ruby:
222 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
223 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
224 sys.exit(1)
225
226 # Set the option for physmem so that it is not allocated any space
227 system.physmem = MemClass(range=AddrRange(options.mem_size),
228 null = True)
229
230 options.use_map = True
231 Ruby.create_system(options, system)
232 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
233
234 for i in xrange(np):
235 ruby_port = system.ruby._cpu_ruby_ports[i]
236
237 # Create the interrupt controller and connect its ports to Ruby
238 # Note that the interrupt controller is always present but only
239 # in x86 does it have message ports that need to be connected
240 system.cpu[i].createInterruptController()
241
242 # Connect the cpu's cache ports to Ruby
243 system.cpu[i].icache_port = ruby_port.slave
244 system.cpu[i].dcache_port = ruby_port.slave
245 if buildEnv['TARGET_ISA'] == 'x86':
246 system.cpu[i].interrupts.pio = ruby_port.master
247 system.cpu[i].interrupts.int_master = ruby_port.slave
248 system.cpu[i].interrupts.int_slave = ruby_port.master
249 system.cpu[i].itb.walker.port = ruby_port.slave
250 system.cpu[i].dtb.walker.port = ruby_port.slave
251else:
252 system.membus = CoherentBus()
253 system.system_port = system.membus.slave
254 CacheConfig.config_cache(options, system)
255 MemConfig.config_mem(options, system)
256
257root = Root(full_system = False, system = system)
258Simulation.run(options, root, system, FutureClass)
| 146 multiprocesses.append(workload.makeLiveProcess())
147 except:
148 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
149 sys.exit(1)
150elif options.cmd:
151 multiprocesses, numThreads = get_processes(options)
152else:
153 print >> sys.stderr, "No workload specified. Exiting!\n"
154 sys.exit(1)
155
156
157(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
158CPUClass.numThreads = numThreads
159
160MemClass = Simulation.setMemClass(options)
161
162# Check -- do not allow SMT with multiple CPUs
163if options.smt and options.num_cpus > 1:
164 fatal("You cannot use SMT with multiple CPUs!")
165
166np = options.num_cpus
167system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
168 mem_mode = test_mem_mode,
169 mem_ranges = [AddrRange(options.mem_size)],
170 cache_line_size = options.cacheline_size)
171
172# Create a top-level voltage domain
173system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
174
175# Create a source clock for the system and set the clock period
176system.clk_domain = SrcClockDomain(clock = options.sys_clock,
177 voltage_domain = system.voltage_domain)
178
179# Create a CPU voltage domain
180system.cpu_voltage_domain = VoltageDomain()
181
182# Create a separate clock domain for the CPUs
183system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
184 voltage_domain =
185 system.cpu_voltage_domain)
186
187# All cpus belong to a common cpu_clk_domain, therefore running at a common
188# frequency.
189for cpu in system.cpu:
190 cpu.clk_domain = system.cpu_clk_domain
191
192# Sanity check
193if options.fastmem:
194 if CPUClass != AtomicSimpleCPU:
195 fatal("Fastmem can only be used with atomic CPU!")
196 if (options.caches or options.l2cache):
197 fatal("You cannot use fastmem in combination with caches!")
198
199if options.simpoint_profile:
200 if not options.fastmem:
201 # Atomic CPU checked with fastmem option already
202 fatal("SimPoint generation should be done with atomic cpu and fastmem")
203 if np > 1:
204 fatal("SimPoint generation not supported with more than one CPUs")
205
206for i in xrange(np):
207 if options.smt:
208 system.cpu[i].workload = multiprocesses
209 elif len(multiprocesses) == 1:
210 system.cpu[i].workload = multiprocesses[0]
211 else:
212 system.cpu[i].workload = multiprocesses[i]
213
214 if options.fastmem:
215 system.cpu[i].fastmem = True
216
217 if options.simpoint_profile:
218 system.cpu[i].simpoint_profile = True
219 system.cpu[i].simpoint_interval = options.simpoint_interval
220
221 if options.checker:
222 system.cpu[i].addCheckerCpu()
223
224 system.cpu[i].createThreads()
225
226if options.ruby:
227 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
228 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
229 sys.exit(1)
230
231 # Set the option for physmem so that it is not allocated any space
232 system.physmem = MemClass(range=AddrRange(options.mem_size),
233 null = True)
234
235 options.use_map = True
236 Ruby.create_system(options, system)
237 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
238
239 for i in xrange(np):
240 ruby_port = system.ruby._cpu_ruby_ports[i]
241
242 # Create the interrupt controller and connect its ports to Ruby
243 # Note that the interrupt controller is always present but only
244 # in x86 does it have message ports that need to be connected
245 system.cpu[i].createInterruptController()
246
247 # Connect the cpu's cache ports to Ruby
248 system.cpu[i].icache_port = ruby_port.slave
249 system.cpu[i].dcache_port = ruby_port.slave
250 if buildEnv['TARGET_ISA'] == 'x86':
251 system.cpu[i].interrupts.pio = ruby_port.master
252 system.cpu[i].interrupts.int_master = ruby_port.slave
253 system.cpu[i].interrupts.int_slave = ruby_port.master
254 system.cpu[i].itb.walker.port = ruby_port.slave
255 system.cpu[i].dtb.walker.port = ruby_port.slave
256else:
257 system.membus = CoherentBus()
258 system.system_port = system.membus.slave
259 CacheConfig.config_cache(options, system)
260 MemConfig.config_mem(options, system)
261
262root = Root(full_system = False, system = system)
263Simulation.run(options, root, system, FutureClass)
|