1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47
48import m5
49from m5.defines import buildEnv
50from m5.objects import *
51from m5.util import addToPath, fatal
52
53addToPath('../common')
54addToPath('../ruby')
55
56import Options
57import Ruby
58import Simulation
59import CacheConfig
60from Caches import *
61from cpu2000 import *
62
63parser = optparse.OptionParser()
64Options.addCommonOptions(parser)
65Options.addSEOptions(parser)
66
67if '--ruby' in sys.argv:
68 Ruby.define_options(parser)
69
70(options, args) = parser.parse_args()
71
72if args:
73 print "Error: script doesn't take any positional arguments"
74 sys.exit(1)
75
76multiprocesses = []
77apps = []
78
79if options.bench:
80 apps = options.bench.split("-")
81 if len(apps) != options.num_cpus:
82 print "number of benchmarks not equal to set num_cpus!"
83 sys.exit(1)
84
85 for app in apps:
86 try:
87 if buildEnv['TARGET_ISA'] == 'alpha':
88 exec("workload = %s('alpha', 'tru64', 'ref')" % app)
89 else:
90 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
91 multiprocesses.append(workload.makeLiveProcess())
92 except:
93 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
94 sys.exit(1)
95elif options.cmd:
96 process = LiveProcess()
97 process.executable = options.cmd
98 process.cmd = [options.cmd] + options.options.split()
99 multiprocesses.append(process)
100else:
101 print >> sys.stderr, "No workload specified. Exiting!\n"
102 sys.exit(1)
103
104
105if options.input != "":
106 process.input = options.input
107if options.output != "":
108 process.output = options.output
109if options.errout != "":
110 process.errout = options.errout
111
112
113# By default, set workload to path of user-specified binary
114workloads = options.cmd
115numThreads = 1
116
117if options.cpu_type == "detailed" or options.cpu_type == "inorder":
118 #check for SMT workload
119 workloads = options.cmd.split(';')
120 if len(workloads) > 1:
121 process = []
122 smt_idx = 0
123 inputs = []
124 outputs = []
125 errouts = []
126
127 if options.input != "":
128 inputs = options.input.split(';')
129 if options.output != "":
130 outputs = options.output.split(';')
131 if options.errout != "":
132 errouts = options.errout.split(';')
133
134 for wrkld in workloads:
135 smt_process = LiveProcess()
136 smt_process.executable = wrkld
137 smt_process.cmd = wrkld + " " + options.options
138 if inputs and inputs[smt_idx]:
139 smt_process.input = inputs[smt_idx]
140 if outputs and outputs[smt_idx]:
141 smt_process.output = outputs[smt_idx]
142 if errouts and errouts[smt_idx]:
143 smt_process.errout = errouts[smt_idx]
144 process += [smt_process, ]
145 smt_idx += 1
146 numThreads = len(workloads)
147
148(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
149CPUClass.clock = '2GHz'
150CPUClass.numThreads = numThreads;
151
152np = options.num_cpus
153
154system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
155 physmem = PhysicalMemory(range=AddrRange("512MB")),
156 membus = Bus(), mem_mode = test_mem_mode)
157
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47
48import m5
49from m5.defines import buildEnv
50from m5.objects import *
51from m5.util import addToPath, fatal
52
53addToPath('../common')
54addToPath('../ruby')
55
56import Options
57import Ruby
58import Simulation
59import CacheConfig
60from Caches import *
61from cpu2000 import *
62
63parser = optparse.OptionParser()
64Options.addCommonOptions(parser)
65Options.addSEOptions(parser)
66
67if '--ruby' in sys.argv:
68 Ruby.define_options(parser)
69
70(options, args) = parser.parse_args()
71
72if args:
73 print "Error: script doesn't take any positional arguments"
74 sys.exit(1)
75
76multiprocesses = []
77apps = []
78
79if options.bench:
80 apps = options.bench.split("-")
81 if len(apps) != options.num_cpus:
82 print "number of benchmarks not equal to set num_cpus!"
83 sys.exit(1)
84
85 for app in apps:
86 try:
87 if buildEnv['TARGET_ISA'] == 'alpha':
88 exec("workload = %s('alpha', 'tru64', 'ref')" % app)
89 else:
90 exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
91 multiprocesses.append(workload.makeLiveProcess())
92 except:
93 print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
94 sys.exit(1)
95elif options.cmd:
96 process = LiveProcess()
97 process.executable = options.cmd
98 process.cmd = [options.cmd] + options.options.split()
99 multiprocesses.append(process)
100else:
101 print >> sys.stderr, "No workload specified. Exiting!\n"
102 sys.exit(1)
103
104
105if options.input != "":
106 process.input = options.input
107if options.output != "":
108 process.output = options.output
109if options.errout != "":
110 process.errout = options.errout
111
112
113# By default, set workload to path of user-specified binary
114workloads = options.cmd
115numThreads = 1
116
117if options.cpu_type == "detailed" or options.cpu_type == "inorder":
118 #check for SMT workload
119 workloads = options.cmd.split(';')
120 if len(workloads) > 1:
121 process = []
122 smt_idx = 0
123 inputs = []
124 outputs = []
125 errouts = []
126
127 if options.input != "":
128 inputs = options.input.split(';')
129 if options.output != "":
130 outputs = options.output.split(';')
131 if options.errout != "":
132 errouts = options.errout.split(';')
133
134 for wrkld in workloads:
135 smt_process = LiveProcess()
136 smt_process.executable = wrkld
137 smt_process.cmd = wrkld + " " + options.options
138 if inputs and inputs[smt_idx]:
139 smt_process.input = inputs[smt_idx]
140 if outputs and outputs[smt_idx]:
141 smt_process.output = outputs[smt_idx]
142 if errouts and errouts[smt_idx]:
143 smt_process.errout = errouts[smt_idx]
144 process += [smt_process, ]
145 smt_idx += 1
146 numThreads = len(workloads)
147
148(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
149CPUClass.clock = '2GHz'
150CPUClass.numThreads = numThreads;
151
152np = options.num_cpus
153
154system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
155 physmem = PhysicalMemory(range=AddrRange("512MB")),
156 membus = Bus(), mem_mode = test_mem_mode)
157
|
163
164 if options.checker:
165 system.cpu[i].addCheckerCpu()
166
167if options.ruby:
168 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
169 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
170 sys.exit(1)
171
172 options.use_map = True
173 Ruby.create_system(options, system)
174 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
175
176 for i in xrange(np):
177 ruby_port = system.ruby._cpu_ruby_ports[i]
178
179 # Create the interrupt controller and connect its ports to Ruby
180 system.cpu[i].createInterruptController()
181 system.cpu[i].interrupts.pio = ruby_port.master
182 system.cpu[i].interrupts.int_master = ruby_port.slave
183 system.cpu[i].interrupts.int_slave = ruby_port.master
184
185 # Connect the cpu's cache ports to Ruby
186 system.cpu[i].icache_port = ruby_port.slave
187 system.cpu[i].dcache_port = ruby_port.slave
188else:
189 system.system_port = system.membus.slave
190 system.physmem.port = system.membus.master
191 CacheConfig.config_cache(options, system)
192
193root = Root(full_system = False, system = system)
194Simulation.run(options, root, system, FutureClass)
| 167
168 if options.checker:
169 system.cpu[i].addCheckerCpu()
170
171if options.ruby:
172 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
173 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
174 sys.exit(1)
175
176 options.use_map = True
177 Ruby.create_system(options, system)
178 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
179
180 for i in xrange(np):
181 ruby_port = system.ruby._cpu_ruby_ports[i]
182
183 # Create the interrupt controller and connect its ports to Ruby
184 system.cpu[i].createInterruptController()
185 system.cpu[i].interrupts.pio = ruby_port.master
186 system.cpu[i].interrupts.int_master = ruby_port.slave
187 system.cpu[i].interrupts.int_slave = ruby_port.master
188
189 # Connect the cpu's cache ports to Ruby
190 system.cpu[i].icache_port = ruby_port.slave
191 system.cpu[i].dcache_port = ruby_port.slave
192else:
193 system.system_port = system.membus.slave
194 system.physmem.port = system.membus.master
195 CacheConfig.config_cache(options, system)
196
197root = Root(full_system = False, system = system)
198Simulation.run(options, root, system, FutureClass)
|