1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29# Simple test script
30#
31# "m5 test.py"
32
33import m5
| 1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29# Simple test script
30#
31# "m5 test.py"
32
33import m5
|
34from m5.objects import *
35import os, optparse, sys
36m5.AddToPath('../common')
37import Simulation
38from Caches import *
39from cpu2000 import *
40
41# Get paths we might need. It's expected this file is in m5/configs/example.
42config_path = os.path.dirname(os.path.abspath(__file__))
43config_root = os.path.dirname(config_path)
44m5_root = os.path.dirname(config_root)
45
46parser = optparse.OptionParser()
47
48# Benchmark options
49parser.add_option("-c", "--cmd",
50 default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
51 help="The binary to run in syscall emulation mode.")
52parser.add_option("-o", "--options", default="",
53 help="The options to pass to the binary, use \" \" around the entire\
54 string.")
55parser.add_option("-i", "--input", default="",
56 help="A file of input to give to the binary.")
57
58execfile(os.path.join(config_root, "common", "Options.py"))
59
60(options, args) = parser.parse_args()
61
62if args:
63 print "Error: script doesn't take any positional arguments"
64 sys.exit(1)
65
66if options.bench:
67 try:
68 if m5.build_env['TARGET_ISA'] != 'alpha':
69 print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
70 sys.exit(1)
71 exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
72 process = workload.makeLiveProcess()
73 except:
74 print >>sys.stderr, "Unable to find workload for %s" % options.bench
75 sys.exit(1)
76else:
77 process = LiveProcess()
78 process.executable = options.cmd
79 process.cmd = [options.cmd] + options.options.split()
80
81
82if options.input != "":
83 process.input = options.input
84
85if options.detailed:
86 #check for SMT workload
87 workloads = options.cmd.split(';')
88 if len(workloads) > 1:
89 process = []
90 smt_idx = 0
91 inputs = []
92
93 if options.input != "":
94 inputs = options.input.split(';')
95
96 for wrkld in workloads:
97 smt_process = LiveProcess()
98 smt_process.executable = wrkld
99 smt_process.cmd = wrkld + " " + options.options
100 if inputs and inputs[smt_idx]:
101 smt_process.input = inputs[smt_idx]
102 process += [smt_process, ]
103 smt_idx += 1
104
105(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
106
107CPUClass.clock = '2GHz'
108
109np = options.num_cpus
110
111system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
112 physmem = PhysicalMemory(range=AddrRange("512MB")),
113 membus = Bus(), mem_mode = test_mem_mode)
114
115system.physmem.port = system.membus.port
116
117if options.l2cache:
118 system.l2 = L2Cache(size='2MB')
119 system.tol2bus = Bus()
120 system.l2.cpu_side = system.tol2bus.port
121 system.l2.mem_side = system.membus.port
122
123for i in xrange(np):
124 if options.caches:
125 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
126 L1Cache(size = '64kB'))
127 if options.l2cache:
128 system.cpu[i].connectMemPorts(system.tol2bus)
129 else:
130 system.cpu[i].connectMemPorts(system.membus)
131 system.cpu[i].workload = process
132
133 if options.fastmem:
134 system.cpu[0].physmem_port = system.physmem.port
135
136root = Root(system = system)
137
138Simulation.run(options, root, system, FutureClass)
| 38from m5.objects import *
39import os, optparse, sys
40m5.AddToPath('../common')
41import Simulation
42from Caches import *
43from cpu2000 import *
44
45# Get paths we might need. It's expected this file is in m5/configs/example.
46config_path = os.path.dirname(os.path.abspath(__file__))
47config_root = os.path.dirname(config_path)
48m5_root = os.path.dirname(config_root)
49
50parser = optparse.OptionParser()
51
52# Benchmark options
53parser.add_option("-c", "--cmd",
54 default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
55 help="The binary to run in syscall emulation mode.")
56parser.add_option("-o", "--options", default="",
57 help="The options to pass to the binary, use \" \" around the entire\
58 string.")
59parser.add_option("-i", "--input", default="",
60 help="A file of input to give to the binary.")
61
62execfile(os.path.join(config_root, "common", "Options.py"))
63
64(options, args) = parser.parse_args()
65
66if args:
67 print "Error: script doesn't take any positional arguments"
68 sys.exit(1)
69
70if options.bench:
71 try:
72 if m5.build_env['TARGET_ISA'] != 'alpha':
73 print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
74 sys.exit(1)
75 exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
76 process = workload.makeLiveProcess()
77 except:
78 print >>sys.stderr, "Unable to find workload for %s" % options.bench
79 sys.exit(1)
80else:
81 process = LiveProcess()
82 process.executable = options.cmd
83 process.cmd = [options.cmd] + options.options.split()
84
85
86if options.input != "":
87 process.input = options.input
88
89if options.detailed:
90 #check for SMT workload
91 workloads = options.cmd.split(';')
92 if len(workloads) > 1:
93 process = []
94 smt_idx = 0
95 inputs = []
96
97 if options.input != "":
98 inputs = options.input.split(';')
99
100 for wrkld in workloads:
101 smt_process = LiveProcess()
102 smt_process.executable = wrkld
103 smt_process.cmd = wrkld + " " + options.options
104 if inputs and inputs[smt_idx]:
105 smt_process.input = inputs[smt_idx]
106 process += [smt_process, ]
107 smt_idx += 1
108
109(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
110
111CPUClass.clock = '2GHz'
112
113np = options.num_cpus
114
115system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
116 physmem = PhysicalMemory(range=AddrRange("512MB")),
117 membus = Bus(), mem_mode = test_mem_mode)
118
119system.physmem.port = system.membus.port
120
121if options.l2cache:
122 system.l2 = L2Cache(size='2MB')
123 system.tol2bus = Bus()
124 system.l2.cpu_side = system.tol2bus.port
125 system.l2.mem_side = system.membus.port
126
127for i in xrange(np):
128 if options.caches:
129 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
130 L1Cache(size = '64kB'))
131 if options.l2cache:
132 system.cpu[i].connectMemPorts(system.tol2bus)
133 else:
134 system.cpu[i].connectMemPorts(system.membus)
135 system.cpu[i].workload = process
136
137 if options.fastmem:
138 system.cpu[0].physmem_port = system.physmem.port
139
140root = Root(system = system)
141
142Simulation.run(options, root, system, FutureClass)
|