1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45from __future__ import print_function
46
47import optparse
48import sys
49import os
50
51import m5
52from m5.defines import buildEnv
53from m5.objects import *
54from m5.util import addToPath, fatal, warn
55
56addToPath('../')
57
58from ruby import Ruby
59
60from common import Options
61from common import Simulation
62from common import CacheConfig
63from common import CpuConfig
64from common import MemConfig
65from common.Caches import *
66from common.cpu2000 import *
67
68def get_processes(options):
69 """Interprets provided options and returns a list of processes"""
70
71 multiprocesses = []
72 inputs = []
73 outputs = []
74 errouts = []
75 pargs = []
76
77 workloads = options.cmd.split(';')
78 if options.input != "":
79 inputs = options.input.split(';')
80 if options.output != "":
81 outputs = options.output.split(';')
82 if options.errout != "":
83 errouts = options.errout.split(';')
84 if options.options != "":
85 pargs = options.options.split(';')
86
87 idx = 0
88 for wrkld in workloads:
89 process = Process(pid = 100 + idx)
90 process.executable = wrkld
91 process.cwd = os.getcwd()
92
93 if options.env:
94 with open(options.env, 'r') as f:
95 process.env = [line.rstrip() for line in f]
96
97 if len(pargs) > idx:
98 process.cmd = [wrkld] + pargs[idx].split()
99 else:
100 process.cmd = [wrkld]
101
102 if len(inputs) > idx:
103 process.input = inputs[idx]
104 if len(outputs) > idx:
105 process.output = outputs[idx]
106 if len(errouts) > idx:
107 process.errout = errouts[idx]
108
109 multiprocesses.append(process)
110 idx += 1
111
112 if options.smt:
113 assert(options.cpu_type == "DerivO3CPU")
114 return multiprocesses, idx
115 else:
116 return multiprocesses, 1
117
118
119parser = optparse.OptionParser()
120Options.addCommonOptions(parser)
121Options.addSEOptions(parser)
122
123if '--ruby' in sys.argv:
124 Ruby.define_options(parser)
125
126(options, args) = parser.parse_args()
127
128if args:
129 print("Error: script doesn't take any positional arguments")
130 sys.exit(1)
131
132multiprocesses = []
133numThreads = 1
134
135if options.bench:
136 apps = options.bench.split("-")
137 if len(apps) != options.num_cpus:
138 print("number of benchmarks not equal to set num_cpus!")
139 sys.exit(1)
140
141 for app in apps:
142 try:
143 if buildEnv['TARGET_ISA'] == 'alpha':
144 exec("workload = %s('alpha', 'tru64', '%s')" % (
145 app, options.spec_input))
146 elif buildEnv['TARGET_ISA'] == 'arm':
147 exec("workload = %s('arm_%s', 'linux', '%s')" % (
148 app, options.arm_iset, options.spec_input))
149 else:
150 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
151 app, options.spec_input))
152 multiprocesses.append(workload.makeProcess())
153 except:
154 print("Unable to find workload for %s: %s" %
155 (buildEnv['TARGET_ISA'], app),
156 file=sys.stderr)
157 sys.exit(1)
158elif options.cmd:
159 multiprocesses, numThreads = get_processes(options)
160else:
161 print("No workload specified. Exiting!\n", file=sys.stderr)
162 sys.exit(1)
163
164
165(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
166CPUClass.numThreads = numThreads
167
168# Check -- do not allow SMT with multiple CPUs
169if options.smt and options.num_cpus > 1:
170 fatal("You cannot use SMT with multiple CPUs!")
171
172np = options.num_cpus
173system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
174 mem_mode = test_mem_mode,
175 mem_ranges = [AddrRange(options.mem_size)],
176 cache_line_size = options.cacheline_size)
177
178if numThreads > 1:
179 system.multi_thread = True
180
181# Create a top-level voltage domain
182system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
183
184# Create a source clock for the system and set the clock period
185system.clk_domain = SrcClockDomain(clock = options.sys_clock,
186 voltage_domain = system.voltage_domain)
187
188# Create a CPU voltage domain
189system.cpu_voltage_domain = VoltageDomain()
190
191# Create a separate clock domain for the CPUs
192system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
193 voltage_domain =
194 system.cpu_voltage_domain)
195
196# If elastic tracing is enabled, then configure the cpu and attach the elastic
197# trace probe
198if options.elastic_trace_en:
199 CpuConfig.config_etrace(CPUClass, system.cpu, options)
200
201# All cpus belong to a common cpu_clk_domain, therefore running at a common
202# frequency.
203for cpu in system.cpu:
204 cpu.clk_domain = system.cpu_clk_domain
205
206if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
207 if buildEnv['TARGET_ISA'] == 'x86':
208 system.kvm_vm = KvmVM()
209 for process in multiprocesses:
210 process.useArchPT = True
211 process.kvmInSE = True
212 else:
213 fatal("KvmCPU can only be used in SE mode with x86")
214
215# Sanity check
216if options.simpoint_profile:
| 1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45from __future__ import print_function
46
47import optparse
48import sys
49import os
50
51import m5
52from m5.defines import buildEnv
53from m5.objects import *
54from m5.util import addToPath, fatal, warn
55
56addToPath('../')
57
58from ruby import Ruby
59
60from common import Options
61from common import Simulation
62from common import CacheConfig
63from common import CpuConfig
64from common import MemConfig
65from common.Caches import *
66from common.cpu2000 import *
67
68def get_processes(options):
69 """Interprets provided options and returns a list of processes"""
70
71 multiprocesses = []
72 inputs = []
73 outputs = []
74 errouts = []
75 pargs = []
76
77 workloads = options.cmd.split(';')
78 if options.input != "":
79 inputs = options.input.split(';')
80 if options.output != "":
81 outputs = options.output.split(';')
82 if options.errout != "":
83 errouts = options.errout.split(';')
84 if options.options != "":
85 pargs = options.options.split(';')
86
87 idx = 0
88 for wrkld in workloads:
89 process = Process(pid = 100 + idx)
90 process.executable = wrkld
91 process.cwd = os.getcwd()
92
93 if options.env:
94 with open(options.env, 'r') as f:
95 process.env = [line.rstrip() for line in f]
96
97 if len(pargs) > idx:
98 process.cmd = [wrkld] + pargs[idx].split()
99 else:
100 process.cmd = [wrkld]
101
102 if len(inputs) > idx:
103 process.input = inputs[idx]
104 if len(outputs) > idx:
105 process.output = outputs[idx]
106 if len(errouts) > idx:
107 process.errout = errouts[idx]
108
109 multiprocesses.append(process)
110 idx += 1
111
112 if options.smt:
113 assert(options.cpu_type == "DerivO3CPU")
114 return multiprocesses, idx
115 else:
116 return multiprocesses, 1
117
118
119parser = optparse.OptionParser()
120Options.addCommonOptions(parser)
121Options.addSEOptions(parser)
122
123if '--ruby' in sys.argv:
124 Ruby.define_options(parser)
125
126(options, args) = parser.parse_args()
127
128if args:
129 print("Error: script doesn't take any positional arguments")
130 sys.exit(1)
131
132multiprocesses = []
133numThreads = 1
134
135if options.bench:
136 apps = options.bench.split("-")
137 if len(apps) != options.num_cpus:
138 print("number of benchmarks not equal to set num_cpus!")
139 sys.exit(1)
140
141 for app in apps:
142 try:
143 if buildEnv['TARGET_ISA'] == 'alpha':
144 exec("workload = %s('alpha', 'tru64', '%s')" % (
145 app, options.spec_input))
146 elif buildEnv['TARGET_ISA'] == 'arm':
147 exec("workload = %s('arm_%s', 'linux', '%s')" % (
148 app, options.arm_iset, options.spec_input))
149 else:
150 exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
151 app, options.spec_input))
152 multiprocesses.append(workload.makeProcess())
153 except:
154 print("Unable to find workload for %s: %s" %
155 (buildEnv['TARGET_ISA'], app),
156 file=sys.stderr)
157 sys.exit(1)
158elif options.cmd:
159 multiprocesses, numThreads = get_processes(options)
160else:
161 print("No workload specified. Exiting!\n", file=sys.stderr)
162 sys.exit(1)
163
164
165(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
166CPUClass.numThreads = numThreads
167
168# Check -- do not allow SMT with multiple CPUs
169if options.smt and options.num_cpus > 1:
170 fatal("You cannot use SMT with multiple CPUs!")
171
172np = options.num_cpus
173system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
174 mem_mode = test_mem_mode,
175 mem_ranges = [AddrRange(options.mem_size)],
176 cache_line_size = options.cacheline_size)
177
178if numThreads > 1:
179 system.multi_thread = True
180
181# Create a top-level voltage domain
182system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
183
184# Create a source clock for the system and set the clock period
185system.clk_domain = SrcClockDomain(clock = options.sys_clock,
186 voltage_domain = system.voltage_domain)
187
188# Create a CPU voltage domain
189system.cpu_voltage_domain = VoltageDomain()
190
191# Create a separate clock domain for the CPUs
192system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
193 voltage_domain =
194 system.cpu_voltage_domain)
195
196# If elastic tracing is enabled, then configure the cpu and attach the elastic
197# trace probe
198if options.elastic_trace_en:
199 CpuConfig.config_etrace(CPUClass, system.cpu, options)
200
201# All cpus belong to a common cpu_clk_domain, therefore running at a common
202# frequency.
203for cpu in system.cpu:
204 cpu.clk_domain = system.cpu_clk_domain
205
206if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
207 if buildEnv['TARGET_ISA'] == 'x86':
208 system.kvm_vm = KvmVM()
209 for process in multiprocesses:
210 process.useArchPT = True
211 process.kvmInSE = True
212 else:
213 fatal("KvmCPU can only be used in SE mode with x86")
214
215# Sanity check
216if options.simpoint_profile:
|
218 fatal("SimPoint/BPProbe should be done with an atomic cpu")
219 if np > 1:
220 fatal("SimPoint generation not supported with more than one CPUs")
221
222for i in xrange(np):
223 if options.smt:
224 system.cpu[i].workload = multiprocesses
225 elif len(multiprocesses) == 1:
226 system.cpu[i].workload = multiprocesses[0]
227 else:
228 system.cpu[i].workload = multiprocesses[i]
229
230 if options.simpoint_profile:
231 system.cpu[i].addSimPointProbe(options.simpoint_interval)
232
233 if options.checker:
234 system.cpu[i].addCheckerCpu()
235
236 system.cpu[i].createThreads()
237
238if options.ruby:
239 Ruby.create_system(options, False, system)
240 assert(options.num_cpus == len(system.ruby._cpu_ports))
241
242 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
243 voltage_domain = system.voltage_domain)
244 for i in xrange(np):
245 ruby_port = system.ruby._cpu_ports[i]
246
247 # Create the interrupt controller and connect its ports to Ruby
248 # Note that the interrupt controller is always present but only
249 # in x86 does it have message ports that need to be connected
250 system.cpu[i].createInterruptController()
251
252 # Connect the cpu's cache ports to Ruby
253 system.cpu[i].icache_port = ruby_port.slave
254 system.cpu[i].dcache_port = ruby_port.slave
255 if buildEnv['TARGET_ISA'] == 'x86':
256 system.cpu[i].interrupts[0].pio = ruby_port.master
257 system.cpu[i].interrupts[0].int_master = ruby_port.slave
258 system.cpu[i].interrupts[0].int_slave = ruby_port.master
259 system.cpu[i].itb.walker.port = ruby_port.slave
260 system.cpu[i].dtb.walker.port = ruby_port.slave
261else:
262 MemClass = Simulation.setMemClass(options)
263 system.membus = SystemXBar()
264 system.system_port = system.membus.slave
265 CacheConfig.config_cache(options, system)
266 MemConfig.config_mem(options, system)
267
268root = Root(full_system = False, system = system)
269Simulation.run(options, root, system, FutureClass)
| 218 fatal("SimPoint/BPProbe should be done with an atomic cpu")
219 if np > 1:
220 fatal("SimPoint generation not supported with more than one CPUs")
221
222for i in xrange(np):
223 if options.smt:
224 system.cpu[i].workload = multiprocesses
225 elif len(multiprocesses) == 1:
226 system.cpu[i].workload = multiprocesses[0]
227 else:
228 system.cpu[i].workload = multiprocesses[i]
229
230 if options.simpoint_profile:
231 system.cpu[i].addSimPointProbe(options.simpoint_interval)
232
233 if options.checker:
234 system.cpu[i].addCheckerCpu()
235
236 system.cpu[i].createThreads()
237
238if options.ruby:
239 Ruby.create_system(options, False, system)
240 assert(options.num_cpus == len(system.ruby._cpu_ports))
241
242 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
243 voltage_domain = system.voltage_domain)
244 for i in xrange(np):
245 ruby_port = system.ruby._cpu_ports[i]
246
247 # Create the interrupt controller and connect its ports to Ruby
248 # Note that the interrupt controller is always present but only
249 # in x86 does it have message ports that need to be connected
250 system.cpu[i].createInterruptController()
251
252 # Connect the cpu's cache ports to Ruby
253 system.cpu[i].icache_port = ruby_port.slave
254 system.cpu[i].dcache_port = ruby_port.slave
255 if buildEnv['TARGET_ISA'] == 'x86':
256 system.cpu[i].interrupts[0].pio = ruby_port.master
257 system.cpu[i].interrupts[0].int_master = ruby_port.slave
258 system.cpu[i].interrupts[0].int_slave = ruby_port.master
259 system.cpu[i].itb.walker.port = ruby_port.slave
260 system.cpu[i].dtb.walker.port = ruby_port.slave
261else:
262 MemClass = Simulation.setMemClass(options)
263 system.membus = SystemXBar()
264 system.system_port = system.membus.slave
265 CacheConfig.config_cache(options, system)
266 MemConfig.config_mem(options, system)
267
268root = Root(full_system = False, system = system)
269Simulation.run(options, root, system, FutureClass)
|