se.py (3514:b166ee5dce91) | se.py (4455:18ff8ee46de8) |
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1# Copyright (c) 2006 The Regents of The University of Michigan | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan |
2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the --- 89 unchanged lines hidden (view full) --- 99 membus = Bus(), mem_mode = test_mem_mode) 100 101system.physmem.port = system.membus.port 102 103for i in xrange(np): 104 if options.caches: 105 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 106 L1Cache(size = '64kB')) | 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the --- 89 unchanged lines hidden (view full) --- 99 membus = Bus(), mem_mode = test_mem_mode) 100 101system.physmem.port = system.membus.port 102 103for i in xrange(np): 104 if options.caches: 105 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 106 L1Cache(size = '64kB')) |
107 system.cpu[i].connectMemPorts(system.membus) | 107 if options.l2cache: 108 system.l2 = L2Cache(size='2MB') 109 system.tol2bus = Bus() 110 system.l2.cpu_side = system.tol2bus.port 111 system.l2.mem_side = system.membus.port 112 system.cpu[i].connectMemPorts(system.tol2bus) 113 else: 114 system.cpu[i].connectMemPorts(system.membus) |
108 system.cpu[i].workload = process 109 110root = Root(system = system) 111 112Simulation.run(options, root, system, FutureClass) | 115 system.cpu[i].workload = process 116 117root = Root(system = system) 118 119Simulation.run(options, root, system, FutureClass) |