se.py (3477:eaf445891a4e) | se.py (3481:14362d3b0756) |
---|---|
1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83 smt_process = LiveProcess() 84 smt_process.executable = wrkld 85 smt_process.cmd = wrkld + " " + options.options 86 if inputs and inputs[smt_idx]: 87 smt_process.input = inputs[smt_idx] 88 process += [smt_process, ] 89 smt_idx += 1 90 | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83 smt_process = LiveProcess() 84 smt_process.executable = wrkld 85 smt_process.cmd = wrkld + " " + options.options 86 if inputs and inputs[smt_idx]: 87 smt_process.input = inputs[smt_idx] 88 process += [smt_process, ] 89 smt_idx += 1 90 |
91(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) |
|
91 | 92 |
92if options.timing: 93 CPUClass = TimingSimpleCPU 94 test_mem_mode = 'timing' 95elif options.detailed: 96 CPUClass = DerivO3CPU 97 test_mem_mode = 'timing' 98else: 99 CPUClass = AtomicSimpleCPU 100 test_mem_mode = 'atomic' 101 | |
102CPUClass.clock = '2GHz' 103 104np = options.num_cpus 105 106system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 107 physmem = PhysicalMemory(range=AddrRange("512MB")), 108 membus = Bus(), mem_mode = test_mem_mode) 109 110system.physmem.port = system.membus.port 111 112for i in xrange(np): | 93CPUClass.clock = '2GHz' 94 95np = options.num_cpus 96 97system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 98 physmem = PhysicalMemory(range=AddrRange("512MB")), 99 membus = Bus(), mem_mode = test_mem_mode) 100 101system.physmem.port = system.membus.port 102 103for i in xrange(np): |
113 if options.caches and not options.standard_switch: | 104 if options.caches and not options.standard_switch and not FutureClass: |
114 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 115 L1Cache(size = '64kB')) 116 system.cpu[i].connectMemPorts(system.membus) 117 system.cpu[i].workload = process 118 119root = Root(system = system) 120 | 105 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 106 L1Cache(size = '64kB')) 107 system.cpu[i].connectMemPorts(system.membus) 108 system.cpu[i].workload = process 109 110root = Root(system = system) 111 |
121Simulation.run(options, root, system) | 112Simulation.run(options, root, system, FutureClass) |