se.py (3448:bb2632fa57dc) | se.py (3476:0e26b5458236) |
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1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 104 unchanged lines hidden (view full) --- 113 114system.physmem.port = system.membus.port 115 116for i in xrange(np): 117 if options.caches and not options.standard_switch: 118 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 119 L1Cache(size = '64kB')) 120 system.cpu[i].connectMemPorts(system.membus) | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 104 unchanged lines hidden (view full) --- 113 114system.physmem.port = system.membus.port 115 116for i in xrange(np): 117 if options.caches and not options.standard_switch: 118 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 119 L1Cache(size = '64kB')) 120 system.cpu[i].connectMemPorts(system.membus) |
121 system.cpu[i].mem = system.physmem | |
122 system.cpu[i].workload = process 123 124root = Root(system = system) 125 126Simulation.run(options, root, system) | 121 system.cpu[i].workload = process 122 123root = Root(system = system) 124 125Simulation.run(options, root, system) |