1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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185 options.use_map = True
186 Ruby.create_system(options, system)
187 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
188
189 for i in xrange(np):
190 ruby_port = system.ruby._cpu_ruby_ports[i]
191
192 # Create the interrupt controller and connect its ports to Ruby
193 system.cpu[i].createInterruptController()
194 system.cpu[i].interrupts.pio = ruby_port.master
195 system.cpu[i].interrupts.int_master = ruby_port.slave
196 system.cpu[i].interrupts.int_slave = ruby_port.master
197
198 # Connect the cpu's cache ports to Ruby
199 system.cpu[i].icache_port = ruby_port.slave
200 system.cpu[i].dcache_port = ruby_port.slave
201 if buildEnv['TARGET_ISA'] == 'x86':
202 system.cpu[i].itb.walker.port = ruby_port.slave
203 system.cpu[i].dtb.walker.port = ruby_port.slave
204else:
205 system.system_port = system.membus.slave
206 system.physmem.port = system.membus.master
207 CacheConfig.config_cache(options, system)
208
209root = Root(full_system = False, system = system)
210Simulation.run(options, root, system, FutureClass)