1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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89if options.output != "":
90 process.output = options.output
91if options.errout != "":
92 process.errout = options.errout
93
94
95# By default, set workload to path of user-specified binary
96workloads = options.cmd
97
98if options.detailed:
99 #check for SMT workload
100 workloads = options.cmd.split(';')
101 if len(workloads) > 1:
102 process = []
103 smt_idx = 0
104 inputs = []
105 outputs = []
106 errouts = []

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119 if inputs and inputs[smt_idx]:
120 smt_process.input = inputs[smt_idx]
121 if outputs and outputs[smt_idx]:
122 smt_process.output = outputs[smt_idx]
123 if errouts and errouts[smt_idx]:
124 smt_process.errout = errouts[smt_idx]
125 process += [smt_process, ]
126 smt_idx += 1
127
128(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
129
130CPUClass.clock = '2GHz'
131CPUClass.numThreads = len(workloads)
132
133np = options.num_cpus
134
135system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
136 physmem = PhysicalMemory(range=AddrRange("512MB")),
137 membus = Bus(), mem_mode = test_mem_mode)
138
139system.physmem.port = system.membus.port

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