1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 86 unchanged lines hidden (view full) ---

95np = options.num_cpus
96
97system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
98 physmem = PhysicalMemory(range=AddrRange("512MB")),
99 membus = Bus(), mem_mode = test_mem_mode)
100
101system.physmem.port = system.membus.port
102
103for i in xrange(np):
104 if options.caches:
105 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
106 L1Cache(size = '64kB'))
107 if options.l2cache:
108 system.l2 = L2Cache(size='2MB')
109 system.tol2bus = Bus()
110 system.l2.cpu_side = system.tol2bus.port
111 system.l2.mem_side = system.membus.port
112 system.cpu[i].connectMemPorts(system.tol2bus)
113 else:
114 system.cpu[i].connectMemPorts(system.membus)
115 system.cpu[i].workload = process
116
117 if options.fastmem:
118 system.cpu[0].physmem_port = system.physmem.port
119
120root = Root(system = system)
121
122Simulation.run(options, root, system, FutureClass)