1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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89if options.output != "":
90 process.output = options.output
91if options.errout != "":
92 process.errout = options.errout
93
94
95# By default, set workload to path of user-specified binary
96workloads = options.cmd
97numThreads = 1
98
99if options.detailed or options.inorder:
100 #check for SMT workload
101 workloads = options.cmd.split(';')
102 if len(workloads) > 1:
103 process = []
104 smt_idx = 0
105 inputs = []
106 outputs = []
107 errouts = []

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120 if inputs and inputs[smt_idx]:
121 smt_process.input = inputs[smt_idx]
122 if outputs and outputs[smt_idx]:
123 smt_process.output = outputs[smt_idx]
124 if errouts and errouts[smt_idx]:
125 smt_process.errout = errouts[smt_idx]
126 process += [smt_process, ]
127 smt_idx += 1
128 numThreads = len(workloads)
129
130(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
131
132CPUClass.clock = '2GHz'
133CPUClass.numThreads = numThreads;
134
135np = options.num_cpus
136
137system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
138 physmem = PhysicalMemory(range=AddrRange("512MB")),
139 membus = Bus(), mem_mode = test_mem_mode)
140
141system.physmem.port = system.membus.port

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